80C86 Datasheet, PDF (26/37 Pages) Intersil Corporation – CMOS 16-Bit Microprocessor

80C86
Waveforms (Continued)
CLK
TCHSV (21)
S2, S1, S0 (EXCEPT HALT)
WRITE CYCLE
AD₁₅-AD₀
82C88
OUTPUTS
SEE NOTES
18, 19
DEN
AMWC OR AIOWC
MWTC OR IOWC
t1
t2
t3 _tW
t4
(23)
TCLAV
TCLDV (33)
TCLAX (24)
TCVNV
(35)
(18) TCLML
(SEE NOTE 20))
(22)
TCLSH
DATA
TCLDX2
(34)
TCVNX (36)
TCLMH
(19)
(18)TCLML
TCLMH (19)
INTA CYCLE
AD15-AD0
(SEE NOTES 21, 22)
(25) TCLAZ
AD15-AD0
RESERVED FOR
CASCADE ADDR
(28) TSVMCH
MCE/PDEN
(30) TCLMCH
DT/R
82C88 OUTPUTS
SEE NOTES 18, 19
INTA
TCLMCL ⁽³²⁾
(41)
TCHDTL
(18) TCLML
(6) TDVCL
POINTER
TCLDX1 (7)
(42) ^TCHDTH
DEN
TCVNV
(35)
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
AD15-AD0
S2
TCLAV
(23)
INVALID ADDRESS
(19) TCLMH
TCVNX
(36)
TCHSV
(21)
TCLSH
(22)
NOTES:
FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)
19. Signals at 82C84A or 82C86 are shown for reference only.
20. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
82C88 CEN.
21. Status inactive in state just prior to t4.
22. Cascade address is valid between first and second INTA cycles.
23. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown
for second INTA cycle.
26
FN2957.3
January 9, 2009