ISL6262A_14 Datasheet, PDF (25/28 Pages) Intersil Corporation – Two-Phase Core Controller(Santa Rosa, IMVP-6+)

ISL6262A
.
2.25
2.2
2.15
2.1
2.05
0
20
40
60
80
100
INDUCTOR TEMPERATURE (°C)
FIGURE 41. LOAD LINE PERFORMANCE WITH NTC
THERMAL COMPENSATION
Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value. This could be
problematic if a load dump were to occur during this time.
This situation would cause the output voltage to rise above
the no load setpoint of the converter and could potentially
damage the CPU.
The L/DCR time constant of the inductor must be matched to
the R_n*C_n time constant as shown in Equation 27.
------^L-------
DCR
=
-^R----ⁿ-----^•----^R-----^S----^E----^Q----^V---
R_n + RS_EQV
•
C_n
(EQ. 27)
Solving for C_n we now have Equation 28.
------^L-------
C_n
=
-----------^D-----^C-----^R-------------
-^R----ⁿ-----^•----^R-----^S----^E----^Q----^V---
R_n + RS_EQV
(EQ. 28)
Note, R_O was neglected. As long as the inductor time
constant matches the C_n, R_n and R_s time constants as given
previously, the transient performance will be optimum. As in
the static droop case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
example of L = 0.36µH with 0.8mΩ DCR, Cn is calculated in
Equation 29.
0_----._--3_---6_----μ_----H_--
C_n = _p----_a----_r---_a---_l--_l--_e----_l--₍--₅₀---_.-^.-₈₀---₂-⁰---₃₀---_K8-----_,---₁----_.-₈----₂---₅---_K-----₎ ≈ 330nF
(EQ. 29)
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the load line, and
slowly increases back to the steady state, the capacitor is
too small and vice versa. It is better to have the capacitor
value a little bigger to cover the tolerance of the inductor to
prevent the output voltage from going lower than the
specification. This cap needs to be a high grade capacitor
like X7R with low tolerance. There is another consideration
in order to achieve better time constant match mentioned
previously. The NPO/COG (class-I) capacitors have only 5%
tolerance and a very good thermal characteristics. But those
capacitors are only available in small capacitance values. In
order to use such capacitors, the resistors and thermistors
surrounding the droop voltage sensing and droop amplifier
has to be resized up to 10X to reduce the capacitance by
10X. But attention has to be paid in balancing the impedance
of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.1mV/A load line, the impedance
needs to be 2.1mΩ. The compensation design has to target
the output impedance of the converter to be 2.1mΩ. There is
a mathematical calculation file available to the user. The
power stage parameters such as L and Cs are needed as
the input to calculate the compensation component values.
Attention has to be paid to the input resistor to the FB pin.
Too high of a resistor will cause an error to the output voltage
regulation because of bias current flowing in the FB pin. It is
better to keep this resistor below 3k when using this file.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6262A through the
matching of the voltages present on the ISEN pins. The
ISL6262A adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. R_L and C_L around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel's inductor. For
optimum performance, R_L is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with R_L to properly compensate the current balance circuit.
ISL6262A uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL6262A forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly equal. Using DCR
current sensing as an example, two errors have to be added
to find the total current imbalance.
1. Mismatch of DCR: If the DCR has a 5% tolerance then
the resistors could mismatch by 10% worst case. If each
phase is carrying 20A then the phase currents mismatch
by 20A*10% = 2A.
2. Mismatch of phase voltages/offset voltage of ISEN pins:
The phase voltages are within 2mV of each other by
25
FN6343.1
December 23, 2008