ISL6262A_14 Datasheet, PDF (19/28 Pages) Intersil Corporation – Two-Phase Core Controller(Santa Rosa, IMVP-6+)

ISL6262A
For overloads exceeding 2.5xthe set level, the PWM outputs
will immediately shut off and PGOOD goes low to maximize
protection due to hard shorts.
In addition, excessive phase unbalance (for example, due to
gate driver failure) will be detected in two-phase operation
and the controller will be shutdown after one millisecond's
detection of the excessive phase current unbalance. The
phase unbalance is detected by the voltage on the ISEN
pins if the difference is greater than 9mV.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after one millisecond in that
condition. The PWM outputs will turn off and PGOOD will go
low. Note that most practical core regulators will have the
overcurrent set to trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
1. For output voltage exceeding the set value by +200mV
for one millisecond, a fault is declared. All of the above
faults have the same action taken: PGOOD is latched low
and the upper and lower power MOSFETs are turned off
so that inductor current will decay through the MOSFET
body diodes. This condition can be reset by bringing
VR_ON low or by bringing VDD below 4V. When these
inputs are returned to their high operating levels, a
soft-start will occur.
2. The second level of overvoltage protection behaves
differently (see Figure 25). If the output exceeds 1.7V, an
OV fault is immediately declared, PGOOD is latched low
and the low-side MOSFETs are turned on. The low-side
MOSFETs will remain on until the output voltage is pulled
down below about 0.85V, at which time all MOSFETs are
turned off. If the output again rises above 1.7V, the
protection process is repeated. This offers the maximum
amount of protection against a shorted high-side
MOSFET while preventing output ringing below ground.
The 1.7V OV is not reset with VR_ON, but requires that
VDD be lowered to reset. The 1.7V OV detector is active
at all times that the controller is enabled including after
one of the other faults occurs so that the processor is
protected against high-side MOSFET leakage while the
MOSFETs are commanded off.
The ISL6262A has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.2V over-temperature
threshold, the VR_TT# pin is pulled low indicating the need
for thermal throttling to the system oversight processor. No
other action is taken within the ISL6262A in response to
NTC pin voltage.
Power Monitor
The power monitor signal is an analog output. Its magnitude
is proportional to the product of V_CCSENSE and the voltage
difference between V_droop and V_O, which is the
programmed voltage droop value, equal to load current
multiplied by the load line impedance (for example 2.1mΩ).
The output voltage of the PMON pin in two-phase design is
given by: V_pmon = V_CCSENSE * (V_droop - V_O) * 17.5. In
always-single-phase design, the output voltage PMON pin is
given by: V_pmon = V_CCSENSE * (V_droop-V_O) * 35.
The power consumed by the CPU can be calculated by:
P_cpu = V_pmon / (17.5 * 0.0021) (Watt), where 0.0021 is the
typical load line slope. The power monitor load regulation is
approximately 7Ω. Within its sourcing/sinking current
capability range, when the power monitor loading changes to
1mA, the output of the power monitor will change to 7mV.
The 7Ω impedance is associated with the layout and
package resistance of PMON inside the IC. In practical
applications, compared to the load resistance on the PMON
pin, 7Ω output impedance contributes no significant error.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6262A uses two slew rates for various modes of
operation. The first is a slow slew rate used to reduce in-rush
current during start-up. It is also used to reduce audible
noise when entering or exiting Deeper Sleep Mode. A faster
slew rate is used to exit out of Deeper Sleep and to enhance
system performance by achieving active mode regulation
more quickly. Note that the SOFT cap current is bidirectional.
The current is flowing into the SOFT capacitor when the
output voltage is commanded to rise and out of the SOFT
capacitor when the output voltage is commanded to fall.
The two slew rates are determined by commanding one of
two current sources onto the SOFT pin. As can be seen in
Figure 36, the SOFT pin has a capacitance to ground. Also,
the SOFT pin is the input to the error amplifier and is,
therefore, the commanded system voltage. Depending on
the state of the system (that is, Start-Up or Active mode) and
the state of the DPRSLPVR pin, one of the two currents
shown in Figure 36 will be used to charge or discharge this
capacitor, thereby controlling the slew rate of the
commanded voltage. These currents can be found under
“SOFT-START CURRENT” on page 4 of the Electrical
Specifications table.
ISL6262A
I_SS
SOFT
C_SOFT
+
V_REF
I₂ ERROR
AMPLIFIER
+
FIGURE 36. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
19
FN6343.1
December 23, 2008