ISL6262A_14 Datasheet, PDF (24/28 Pages) Intersil Corporation – Two-Phase Core Controller(Santa Rosa, IMVP-6+)

ISL6262A
R_droop
=
G₁
(T
)
•
-^D----^C-----^R-----²---⁵-
2
•
(1
+
0.00393 *(T-25) )
•
k_dr
oo
p
am
p
(EQ. 20)
To achieve the droop value independent from the
temperature of the inductor, it is equivalently expressed by
Equation 21.
G₁(T) • (1 + 0.00393*(T-25)) ≅ G_{1t arget}
(EQ. 21)
The non-inverting droop amplifier circuit has the gain
K_droopamp expressed as:
k_droopamp
=
1
+
-^R----^d---^r---^p---²-
R_drp1
G_1target is the desired gain of Vn over I_OUT • DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described by Equation 22.
G₁(T)
=
-----------------^G----¹----^t--^a---^r--^g---^e---^t----------------
(1 + 0.00393*(T-25))
(EQ. 22)
For the G_1target = 0.76:
R_ntc = 10kΩ with b = 4300,
R_series = 2.61kΩ, and
R_par = 11kΩ
RS_EQV = 1825Ω generates a desired G1, close to the
feature specified in Equation 22.
The actual G1 at +25°C is 0.769. For different G1 and NTC
thermistor preferences, the design file to generate the proper
value of R_ntc, R_series, R_par, and RS_EQV is provided by
Intersil.
Then, the individual resistors from each phase to the VSUM
node, labeled R_S1 and R_S2 in Figure 37, are then given by
Equation 23.
R_S = 2 • RS_EQV
(EQ. 23)
So, R_s = 3650Ω. Once we know the attenuation of the R_S
and R_N network, we can then determine the droop amplifier
gain required to achieve the load line. Setting
R_drp1 = 1k_1%, then R_drp2 can be found using Equation 24.
Rdrp2
=
⎛
⎝
----------²-----^•----^R-----^d---^r--^o----^o---^p-----------
DCR • G1(25°C)
–
1_⎠⎞
• R_drp1
(EQ. 24)
Droop Impedance (R_droop) = 0.0021 (V/A) as per the Intel
IMVP-6+ specification, DCR = 0.0008Ω typical for a 0.36µH
inductor, R_drp1 = 1kΩ and the attenuation gain (G1) = 0.77,
R_drp2 is then given by Equation 25.
Rdrp2
=
⎛
⎝
0^----.^-0^-2---0^--•-0^---R-8^---d-•^---r--0^o---.^o--7^--p-6^---9^--
–
1_⎠⎞
• 1kΩ ≈ 5.82kΩ
(EQ. 25)
Note, we choose to ignore the R_O resistors because they do
not add significant error.
These designed values in R_n network are very sensitive to
the layout and coupling factor of the NTC to the inductor. As
only one NTC is required in this application, this NTC should
be placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should be going
directly to the inductor pads.
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
R_drp2 to obtain the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 2.1mV/A load line should be adjusted by R_drp2 based
on maximum current, (not based on small current steps like
10A), as the droop gain might vary between each 10A step.
Basically, if the max current is 40A, the required droop
voltage is 84mV. The user should have 40A load current on
and look for 84mV droop. If the drop voltage is less than
84mV, for example 80mV, the new value will be calculated
by: using Equation 26.
R d r p 2 _new
=
8_----4_----m_-----V_--
80 m V
(Rdrp
1
+
Rdrp2
)
–
Rdrp1
(EQ. 26)
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the previous example, the resistance on the DFB pin is
R_drp1 in parallel with R_drp2, that is, 1k in parallel with 5.82k
or 853Ω. The resistance on the VSUM pin is R_n in parallel
with RS_EQV or 5.87k in parallel with 1.825k or 1392Ω. The
mismatch in the effective resistances is 1404 - 53 = 551Ω.
Do not let the mismatch get larger than 600Ω. To reduce the
mismatch, multiply both R_drp1 and R_drp2 by the appropriate
factor. The appropriate factor in the example is
1404/853 = 1.65. In summary, the predicted load line with
the designed droop network parameters based on the
Intersil design tool is shown in Figure 41
24
FN6343.1
December 23, 2008