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ISL12027_10 Datasheet, PDF (25/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM
ISL12027, ISL12027A
.
TABLE 10. I2C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (Shaded Row is same as X12028 operation)
MODE
SBIB
BIT
BSW
BIT
VBAT
I2C ACTIVE IN
SWITCHOVER BATTERY
VOLTAGE
BACKUP?
EE PROM WRITE/
READ IN BATTERY
BACKUP?
FREQ/IRQ
ACTIVE?
NOTES
A
0
0 Standard Mode,
NO
VTRIP = 2.2V
typ
Default for
ISL12027A
NO
N/A
Operation of I2C bus down to VDD =VRESET,
then below that no communications. Battery
switchover at VTRIP.
B
0
(X12028
mode)
C
1
D
1
1 Legacy Mode, YES, only if
VDD < VBAT VBAT > VRESET
Default for
ISL12027
0 Standard Mode,
NO
VTRIP = 2.2V
typ
1 Legacy Mode,
NO
VDD < VBAT
YES
NO
NO
Yes
YES
YES
Operation of I2C bus into battery backup
mode, but only for
VBAT > VDD > VRESET.
Bus must have pull-ups to VBAT. No
non-volatile writes with VBAT > VDD
Operation of I2C bus down to VDD = VRESET,
then below that no communications. Battery
switchover at VTRIP.
Operation of I2C busdown to VRESET or
VBAT, whichever is higher.
.
VDD
VBAT (3.0V)
VRESET (2.63V)
VTRIP
(2.2V)
tPURST
RESET
IBAT
I2C Bus Active
(VDD POWER, VBAT NOT CONNECTED)
(BATTERY BACKUP MODE)
FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C
VDD
VBAT (3.0V)
VRESET (2.63V)
VTRIP
(2.2V)
tPURST
RESET
IBAT
25
I2C BUS ACTIVE
FIGURE 30. RESET OPERATION IN MODE D
(BATTERY BACKUP MODE)
FN8232.8
August 12, 2010