ISL12027_10 Datasheet, PDF (2/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12027, ISL12027A
Pin Descriptions
PIN NUMBER
SOIC
TSSOP
1
3
2
4
3
5
4
6
5
7
6
8
7
1
8
2
SYMBOL
BRIEF DESCRIPTION
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal.
RESET
RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period
has expired or that the voltage has dropped below a fixed V_TRIP threshold. It is an open drain active LOW
output. Recommended value for the pull-up resistor is 5kΩ. If unused, connect to ground.
GND Ground.
SDA
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
V_BAT
V_DD
This input provides a backup supply voltage to the device. V_BAT supplies power to the device in the event
that the V_DD supply fails. This pin should be tied to ground if not used.
Power Supply.
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
V_BAT TRIP POINT BSW BIT DEFAULT
(V)
SETTING
V_RESET
VOLTAGE TEMP. RANGE
(V)
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL12027IB27Z
12027 IB27Z
V_DD < V_BAT
BSW = 1
2.63
-40 to +85 8 Ld SOIC M8.15
ISL12027IB27AZ 12027 IB27AZ
V_DD < V_BAT
BSW = 1
2.92
-40 to +85 8 Ld SOIC M8.15
ISL12027IB30AZ 12027 IB30AZ
V_DD < V_BAT
BSW = 1
3.09
-40 to +85 8 Ld SOIC M8.15
ISL12027IBZ
12027 IBZ
V_DD < V_BAT
BSW = 1
4.38
-40 to +85 8 Ld SOIC M8.15
ISL12027IBAZ
12027 IBAZ
V_DD < V_BAT
BSW = 1
4.64
-40 to +85 8 Ld SOIC M8.15
ISL12027IV27Z
2027 I27Z
V_DD < V_BAT
BSW = 1
2.63
-40 to +85 8 Ld TSSOP M8.173
ISL12027IV27AZ 2027 27AZ
V_DD < V_BAT
BSW = 1
2.92
-40 to +85 8 Ld TSSOP M8.173
ISL12027IV30AZ 2027 30AZ
V_DD < V_BAT
BSW = 1
3.09
-40 to +85 8 Ld TSSOP M8.173
ISL12027IVZ
2027 IVZ
V_DD < V_BAT
BSW = 1
4.38
-40 to +85 8 Ld TSSOP M8.173
ISL12027IVAZ
2027 IVAZ
V_DD < V_BAT
BSW = 1
4.64
-40 to +85 8 Ld TSSOP M8.173
ISL12027AIB27Z 12027A IB27Z
V_DD < V_BAT
BSW = 0
2.63
-40 to +85 8 Ld SOIC M8.15
ISL12027AIV27Z 2027A I27Z
V_DD < V_BAT
BSW =0
2.63
-40 to +85 8 Ld TSSOP M8.173
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12027, ISL12027A. For more information on MSL please see
techbrief TB363.
2
FN8232.8
August 12, 2010