ISL12027_10 Datasheet, PDF (16/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12027, ISL12027A
Standard Mode Power Switchover
• Normal Operating Mode (V_DD) to Battery Backup Mode
(V_BAT)
To transition from the V_DD to V_BAT mode, both of the
following conditions must be met:
• Condition 1:
V_DD < V_BAT - V_BATHYS
where V_BATHYS ≈ 50mV
• Condition 2:
V_DD < V_TRIP
where V_TRIP ≈ 2.2V
• Battery Backup Mode (V_BAT) to Normal Mode (V_DD)
The ISL12027 device will switch from the V_BAT to V_DD mode
when one of the following conditions occurs:
• Condition 1:
V_DD > V_BAT + V_BATHYS
where V_BATHYS ≈ 50mV
• Condition 2:
V_DD > V_TRIP + V_TRIPHYS
where V_TRIPHYS ≈ 30mV
There are two discrete situations that are possible when
using Standard Mode: V_BAT < V_TRIP and V_BAT > V_TRIP.
These two power control situations are illustrated in
Figures 13 and 14.
BATTERY BACKUP
MODE
V_DD
V_TRIP
V_BAT
2.2V
1.8V
V_BAT - V_BATHYS
V_BAT + V_BATHYS
FIGURE 13. BATTERY SWITCHOVER WHEN V_BAT < V_TRIP
V_DD
V_BAT
V_TRIP
V_TRIP
BATTERY BACKUP
MODE
3.0V
2.2V
V_TRIP + V_TRIPHYS
FIGURE 14. BATTERY SWITCHOVER WHEN V_BAT > V_TRIP
OPTION 2 -LEGACY POWER CONTROL MODE
(ISL12027 DEFAULT)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from V_DD to V_BAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the V_BAT voltage is
higher than V_DD, then the device will enter battery back up
and unless the battery is disconnected or the voltage
decreases, the device will no longer operate from V_DD. If that
is the situation on initial power-up, then I²C communication
may not be possible. For these applications, the ISL12027A
should be used.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1”.
• Normal Mode (V_DD) to Battery Backup Mode (V_BAT)
To transition from the V_DD to V_BAT mode, the following
conditions must be met:
V_DD < V_BAT - V_BATHYS
• Battery Backup Mode (V_BAT) to Normal Mode (V_DD)
The device will switch from the V_BAT to V_DD mode when the
following condition occurs:
V_DD > V_BAT +V_BATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15.
V_BAT
V_DD
OFF
VOLTAGE
ON
IN
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
Power On Reset
Application of power to the ISL12027 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
• It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V_DD exceeds the device V_RESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
NOTE: If the V_BAT voltage drops below the data sheet
minimum of 1.8V and the V_DD power cycles to 0V then back
to V_DD voltage, then the RESET output may stay low and the
I²C communications will not operate. The V_BAT and V_DD
power will need to be cycled to 0V together to allow normal
operation again.
16
FN8232.8
August 12, 2010