ISL6312 Datasheet, PDF (24/35 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10,VR11, and AMD Applications

ISL6312
Fault Monitoring and Protection
The ISL6312 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power good signal.
VRSEL
VDAC
OVPSEL
+175mV,
+250mV,
+350mV
V_OVP
-
OCL
+
170µA
I₁
REPEAT FOR
EACH CHANNEL
-
OCP
+
125µA
I_AVG
SOFT-START, FAULT
AND CONTROL LOGIC
VSEN
+
x1
-
RGND
-
OV
+
-
UV
+
PGOOD
VDIFF
0.60 x DAC _{ISL6312 INTERNAL CIRCUITRY}
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6312 is regulating the
output voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied to a +5V source
through a resistor.
During shutdown and soft-start PGOOD pulls low and
releases high after a successful soft-start and the output
voltage is operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected or when the controller is disabled by a reset from
EN, EN_PH4, POR, or one of the no-CPU VID codes. In the
event of an overvoltage or overcurrent condition, the
controller latches off and PGOOD will not return high until
after a successful soft-start. In the case of an undervoltage
event, PGOOD will return high when the output voltage
returns to within the undervoltage.
Overvoltage Protection
The ISL6312 constantly monitors the sensed output voltage
on the VDIFF pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level
actions are taken by the ISL6312 to protect the
microprocessor load. The overvoltage protection trip level
changes depending on what mode of operation the controller
is in and what state the OVPSEL and VRSEL pins are in.
Tables 6 and 7 list what the OVP trip levels are under all
conditions.
At the inception of an overvoltage event, LGATE1, LGATE2
and LGATE3 are commanded high, PWM4 is commanded
low, and the PGOOD signal is driven low. This turns on the
all of the lower MOSFETs and pulls the output voltage below
a level that might cause damage to the load. The LGATE
outputs remain high and PWM4 remains low until VDIFF falls
100mV below the OVP threshold that tripped the overvoltage
protection circuitry. The ISL6312 will continue to protect the
load in this fashion as long as the overvoltage condition
recurs. Once an overvoltage condition ends the ISL6312
latches off, and must be reset by toggling EN, or through
POR, before a soft-start can be reinitiated.
TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS
MODE OF
OPERATION
OVPSEL PIN OPEN OVPSEL PIN TIED
OR TIED TO GND
TO VCC
Soft-Start
(TD1 and TD2)
1.280V and
VDAC + 175mV
(higher of the two)
1.280V and
VDAC + 350mV
(higher of the two)
Soft-Start
(TD3 and TD4)
VDAC + 175mV
VDAC + 350mV
Normal Operation
VDAC + 175mV
VDAC + 350mV
TABLE 7. AMD OVP THRESHOLDS
MODE OF
OPERATION
OVPSEL PIN OPEN OVPSEL PIN TIED
OR TIED TO GND
TO VCC
Soft-Start
2.200V and
VDAC + 250mV
(higher of the two)
2.200V and
VDAC + 350mV
(higher of the two)
Normal Operation
VDAC + 250mV
VDAC + 350mV
One exception that overrides the overvoltage protection
circuitry is a dynamic VID transition in AMD modes of
operation. If a new VID code is detected during normal
operation, the OVP protection circuitry is disabled from the
beginning of the dynamic VID transition, until 50µs after the
internal DAC reaches the final VID setting. This is the only
time during operation of the ISL6312 that the OVP circuitry is
not active.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6312 is designed to protect the load from any overvoltage
events that may occur. This is accomplished by means of an
internal 10kΩ resistor tied from PHASE to LGATE, which
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FN9289.5
February 25, 2010