ISL6312 Datasheet, PDF (20/35 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10,VR11, and AMD Applications

ISL6312
-
V_OFS
+
FB
R_FB
VDIFF
I_OFS
1:1
CURRENT
MIRROR
E/A
REF
I_OFS
VCC
R_OFS
-
1.6V
+
OFS
ISL6312
VCC
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
+
V_OFS
-
FB
R_FB
VDIFF
I_OFS
VCC
E/A
REF
1:1
CURRENT
MIRROR
I_OFS
R_OFS
OFS
ISL6312
+
0.4V
-
GND
GND
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6312 to
do this by making changes to the VID inputs. The ISL6312 is
required to monitor the DAC inputs and respond to on-the-fly
VID changes in a controlled manner, supervising a safe output
voltage transition without discontinuity or disruption. The DAC
mode the ISL6312 is operating in determines how the controller
responds to a dynamic VID change.
INTEL DYNAMIC VID TRANSITIONS
When in Intel VR10 or VR11 mode the ISL6312 checks the
VID inputs on the positive edge of an internal 3MHz clock. If
a new code is established and it remains stable for 3
consecutive readings (1ms to 1.33ms), the ISL6312
recognizes the new code and changes the internal DAC
reference directly to the new level. The Intel processor
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VR10 and VR11 settings, the ISL6312 will immediately
change the internal DAC reference to the new requested
value as soon as the request is validated, which means the
fastest recommended rate at which a bit change can occur is
once every 2ms. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
overvoltage events.
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
an internal 1kΩ resistor between the DAC and the REF pin,
and the external capacitor CREF, between the REF pin and
ground. The selection of CREF is based on the time duration
for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every TVID, the relationship between CREF and TVID is
given by Equation 14.
C_REF = 0.001(S) ⋅ T_VID
(EQ. 14)
As an example, for a VID step change rate of 5ms per bit,
the value of CREF is 5600pF based on Equation 14.
AMD DYNAMIC VID TRANSITIONS
When running in AMD 5-bit or 6-bit modes of operation, the
ISL6312 responds differently to a dynamic VID change then
when in Intel VR10 or VR11 mode. In the AMD modes the
ISL6312 still checks the VID inputs on the positive edge of
an internal 3MHz clock. In these modes the VID code can be
changed by more than a 1-bit step at a time. If a new code is
established and it remains stable for 3 consecutive readings
(1ms to 1.33ms), the ISL6312 recognizes the change and
begins slewing the DAC in 6.25mV steps at a stepping
frequency of 330kHz until the VID and DAC are equal. Thus,
the total time required for a VID change, tDVID, is dependent
only on the size of the VID change (DVVID).
The time required for a ISL6312-based converter in AMD
5-bit DAC configuration to make a 1.1V to 1.5V reference
voltage change is about 194ms, as calculated using
Equation 15.
t_DVID
=
------------¹-------------
330 × 10³
⋅
⎛
⎝
0^---Δ-.^-0^-V---0^--V-6^--I-2^-D---5^{--⎠⎞}
(EQ. 15)
In order to ensure the smooth transition of output voltage
during an AMD VID change, a VID step change smoothing
network is required. This network is composed of an internal
1kΩ resistor between the DAC and the REF pin, and the
external capacitor C_REF, between the REF pin and ground.
For AMD VID transitions C_REF should be a 1000pF
capacitor.
20
FN9289.5
February 25, 2010