ISL6232 Datasheet, PDF (23/25 Pages) Intersil Corporation – High Efficiency System Power Supply Controller for Notebook Computers

ISL6232
Vo
R2
C3
V _{FB -}
V _REF
GM
+
V _COMP
R1
C2
C1
FIGURE 33. TYPE II COMPENSATOR
Figure 33 shows the type II compensator and its transfer
function is expressed as Equation 29:
S)=
-^vˆ---c_vˆ---^oF---^m-_B----^p- =
-------^g----^m---------
C₁ + C₂
⎝⎛_---¹_{-----+------ω--------c-}^S-----_z-------1^---⎠⎞_----⎝⎛_--¹_{-----+------ω---------c}^S------_z^------₂^----⎠⎞_-
S
⎛
⎝
1
+
ω^----S-_c^---_p^{-⎠⎞}
(EQ. 29)
where:
ω_cz1
=
-------¹-------
R₁C₁
,
ω_cz2
=
-------¹------- ,
R₂C₃
ω_c
p
=
-^C-----¹-----+----^C-----²--
R₁C₁C₂
COMPENSATOR DESIGN GOAL
High DC gain
Loop bandwidth f_c:
⎛
⎝
1_--
4
t
o
1^--1--0^{--⎠⎞}
f_s
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
Put compensator zero
ω_cz1=
(
1
t
o
3
)
-------¹-------
R_oC_o
Put one compensator pole at zero frequency to achieve high
DC gain, and put another compensator pole at either esr
zero frequency or half switching frequency, whichever is
lower. ω_CZ2 is an internal zero due to 8pF and 600kΩ.
The loop gain T_v(S) at cross over frequency of f_c has unity
gain. Therefore, the compensator resistance R₁ is
determined by Equation 30.
R₁
=
2_----π_----f_--c---V_----o----C_----o----R_----T--
g_mV_FB
(EQ. 30)
where g_m is the trans-conductance of the voltage error
amplifier. Compensator capacitor C₁ is then given by
Equation 31.
C₁
=
--------¹---------
R₁ω_cz
,C₂
=
------------¹------------
2πR₁f_esr
(EQ. 31)
Example: V_IN = 12V, V_o = 5V, I_o = 5A, f_s = 300kHz,
C_o = 180µF/12mΩ, L = 6.8µH, g_m = 100µs, R_T = 0.128
(R_cs = 8mΩ, A_c = 16), V_FB = 0.8V, S_e = 1.5×10⁵V/s,
S_n = 1.318×10⁵V/s, f_c = 45kHz, then compensator
resistance R₁ = 400kΩ.
Put the compensator zero at 1.5kHz (~1.5x C_oR_o), and put
the compensator pole at esr zero which is 49kHz. The
compensator capacitors are:
C₁ = 270pF, C₂ = 10pF (There is approximately 8pF
parasitic capacitance from V_COMP to GND; Therefore, C₂
optional).
Figure shows the simulated voltage loop gain. It is shown
that it has 30kHz loop bandwidth with 85° phase margin and
20dB gain margin.
60
40
20
V_LOOP
0
-20
-40
-60
100
1·10³
1·10⁴
1·10⁵
1·10⁶
FREQUENCY (Hz)
110
85
V_LOOP
60
35
10
-15
-40
100
1·10³
1·10⁴
1·10⁵
FIGURE 34. SIMULATED LOOP GAIN
1·10⁶
12V Auxiliary Supply
A flyback transformer, or coupled inductor can be substituted
for the inductor in 5V or 3.3V supply to generate an 12V
auxiliary output as shown in Figure 35, which can be used to
drive N-channel MOSFETs. The ISL6232 is particularly well
suited for such applications because it can be configured in
ultrasonic or forced PWM mode to ensure good load
regulation when the main supplies are in light load
conditions. An additional post-regulation circuit can be used
to improve load regulation if necessary.
23
FN9116.1
April 20, 2009