ISL6322_07 Datasheet, PDF (22/41 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

ISL6322
AMD Dynamic VID Transitions
When running in AMD 5-bit or 6-bit modes of operation, the
ISL6322 responds differently to a dynamic VID change than
when in Intel VR10 or VR11 mode. In the AMD modes, the
ISL6322 still checks the VID inputs on the positive edge of
an internal 3MHz clock. In these modes the VID code can be
changed by more than a 1-bit step at a time. If a new code is
established and it remains stable for 3 consecutive readings
(1μs to 1.33μs), the ISL6322 recognizes the change and
begins slewing the DAC in 6.25mV steps at a stepping
frequency of 330kHz until the VID and DAC are equal. Thus,
the total time required for a VID change, t_DVID, is dependent
only on the size of the VID change (ΔV_VID).
The time required for a ISL6322-based converter in AMD 5-bit
DAC configuration to make a 1.1V to 1.5V reference voltage
change is about 194μs, as calculated using the following
equation.
t_DVID
=
------------¹-------------
330 × 10³
⋅
⎛
⎝
0^---Δ-.^-0^-V---0^--V-6^--I-2^-D---5^{--⎠⎞}
(EQ. 15)
In order to ensure the smooth transition of output voltage
during an AMD VID change, a VID step change smoothing
network is required. This network is composed of an internal
1kΩ resistor between the DAC and the REF pin, and the
external capacitor C_REF, between the REF pin and ground.
For AMD VID transitions C_REF should be a 1000pF
capacitor.
User Selectable Adaptive Deadtime Control
Techniques
The ISL6322 integrated drivers incorporate two different
adaptive deadtime control techniques, which the user can
choose between. Both of these control techniques help to
minimize deadtime, resulting in high efficiency from the reduced
freewheeling time of the lower MOSFET body-diode
conduction, and both help to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
The difference between the two adaptive deadtime control
techniques is the method in which they detect that the lower
MOSFET has transitioned off in order to turn on the upper
MOSFET. The state of the internal I²C registers determines
which of the two control techniques is active (see pages 27
through 31 for details of controlling deadtime control with
I²C). The default setting is PHASE Detect. If the PHASE
Detect Scheme is chosen, the voltage on the PHASE pin is
monitored to determine if the lower MOSFET has
transitioned off or not. Choosing the LGATE Detect Scheme
instructs the controller to monitor the voltage on the LGATE
pin to determine if the lower MOSFET has turned off or not.
For both schemes, the method for determining whether the
upper MOSFET has transitioned off in order to signal to turn
on the lower MOSFET is the same.
PHASE DETECT
For the PHASE detect scheme, during turn-off of the lower
MOSFET, the PHASE voltage is monitored until it reaches a
-0.3V/+0.8V (forward/reverse inductor current). At this time the
UGATE is released to rise. An auto-zero comparator is used to
correct the r_DS(ON) drop in the phase voltage preventing false
detection of the -0.3V phase level during r_DS(ON) conduction
period. In the case of zero current, the UGATE is released after
35ns delay of the LGATE dropping below 0.5V. When LGATE
first begins to transition low, this quick transition can disturb the
PHASE node and cause a false trip, so there is 20ns of
blanking time once LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
LGATE DETECT
For the LGATE detect scheme, during turn-off of the lower
MOSFET, the LGATE voltage is monitored until it reaches
1.75V. At this time the UGATE is released to rise.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from the following equation:
C _{B O O T _CAP}
≥
----------^Q-----^G----^A----^T----^E----------
Δ V_{B O O T _CAP}
Q_GATE=
Q_{-----G-----1----}⋅_---P_-----V_----C_-----C_---
V_GS1
⋅
N_Q1
(EQ. 16
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
22
FN6328.1
February 15, 2007