ISL6322_07 Datasheet, PDF (21/41 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications

ISL6322
Output-Voltage Offset Programming
The ISL6322 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R_OFS, from the OFS
pin to VCC or GND. When R_OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into the FB pin.
If R_OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I_OFS flows out of the FB pin. The
offset current flowing through the resistor between VDIFF
and FB will generate the desired offset voltage which is
equal to the product (I_OFS x R_FB). These functions are
shown in Figures 7 and 8.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Negative Offset (connect R_OFS to GND):
R_OFS
=
--⁰---^.--⁴-----^â‹---^R----^F----^B---
V_OFFSET
(EQ. 12)
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
--¹---^.--⁶-----^â‹---^R----^F----^B---
V_OFFSET
(EQ. 13)
-
V_OFS
+
FB
R_FB
VDIFF
I_OFS
1:1
CURRENT
MIRROR
E/A
REF
I_OFS
VCC
R_OFS
-
1.6V
+
OFS
ISL6322
VCC
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6322
to do this by making changes to the VID inputs. The ISL6322
is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The DAC mode the ISL6322 is operating in
determines how the controller responds to a dynamic VID
change.
+
V_OFS
-
FB
R_FB
VDIFF
I_OFS
VCC
E/A
REF
1:1
CURRENT
MIRROR
I_OFS
R_OFS
OFS
ISL6322
+
0.4V
-
GND
GND
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
INTEL DYNAMIC VID TRANSITIONS
When in Intel VR10 or VR11 mode, the ISL6322 checks the
VID inputs on the positive edge of an internal 3MHz clock. If
a new code is established and it remains stable for 3
consecutive readings (1μs to 1.33μs), the ISL6322
recognizes the new code and changes the internal DAC
reference directly to the new level. The Intel processor
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VR10 and VR11 settings, the ISL6322 will immediately
change the internal DAC reference to the new requested
value as soon as the request is validated, which means the
fastest recommended rate at which a bit change can occur is
once every 2μs. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
overvoltage events.
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
an internal 1kΩ resistor between the DAC and the REF pin,
and the external capacitor C_REF, between the REF pin and
ground. The selection of C_REF is based on the time duration
for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1 bit every T_VID, the relationship between C_REF and T_VID is
given by Equation 14.
C_REF = 0.001(S) ⋅ T_VID
(EQ. 14)
As an example, for a VID step change rate of 5μs per bit, the
value of C_REF is 5600pF based on Equation 14.
21
FN6328.1
February 15, 2007