ISL28118_15 Datasheet, PDF (22/29 Pages) Intersil Corporation – 40V Precision Single-Supply, Rail-to-rail Output, Low-power Operational Amplifiers

ISL28118, ISL28218
*ISL28118_218 Macromodel - covers
following *products
*ISL28118
*ISL28218
*
*Revision History:
* Revision B, LaFontaine January 22 2014
* Model for Noise, supply currents, CMRR
*120dB f = 40kHz, AVOL 136dB f = 0.5Hz
* SR = 1.2V/us, GBWP 4MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
characteristics *under a wide range of
external circuit *configurations using
compatible simulation *platforms – such as
iSim PE.
*
*Device performance features supported by
this *model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate,
*Input and Output Headroom limits to I/O
*voltage swing,
*Supply current at nominal specified supply
*voltages,
*
*Device performance features NOT
supported *by this model:
*Harmonic distortion effects,
*Output current limiting (current will limit at
*40mA),
*Disable operation (if any),
*Thermal effects and/or over-temperature
*parameter variation,
*Limited performance variation vs. supply
*voltage is modeled,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging,
*Load current reflected into the power supply
*current.
* source ISL28118_218 SPICEmodel
*
* Connections:
+input
*
| -input
*
| | +Vsupply
*
| | | -Vsupply
*
| | | | output
.subckt ISL28118_218 Vin+ Vin-V₊ V_- VOUT
* source ISL28118_218_presubckt_0
*
*Voltage Noise
E_En
VIN+ 6 2 0 0.3
D_D13
1 2 DN
D_D14
1 2 DN
V_V7
1 0 0.1
V_V8
4 0 0.1
R_R17
2 0 750
*R_R18
3 0 750
*
*Input Stage
Q_Q6
11 10 9 PNP_input
Q_Q7
8 7 9 PNP_input
Q_Q8
V-- VIN- 7 PNP_LATERAL
Q_Q9
V-- 12 10 PNP_LATERAL
I_I1
V++ 9 DC 80e-6
I_I2
V++ 7 DC 54E-6
I_I3
V++ 10 DC 54E-6
I_IOS
6 VIN- DC 4e-9
D_D1
7 10 DBREAK
D_D2
10 7 DBREAK
R_R1
5 6 5e11
R_R2
VIN- 5 5e11
R_R3
V-- 8 1000
R_R4
V-- 11 1000
C_Cin1
V-- VIN- 4.02e-12
C_Cin2
V-- 6 4.02e-12
C_CinDif
6 VIN- 1.33E-12
*
*1st Gain Stage
G_G1
V++ 14 8 11 0.65897
G_G2
V-- 14 8 11 0.65897
V_V1
13 14 -0.91
V_V2
14 15 -0.96
D_D3
13 V++ DX
D_D4
V-- 15 DX
R_R5
14 V++ 1
R_R6
V-- 14 1
*
*2nd Gain Stage
G_G3
V++ VG 14 VMID 1.69138e-3
G_G4
V-- VG 14 VMID 1.69138e-3
V_V3
16 VG -0.91
V_V4
VG 17 -0.96
D_D5
16 V++ DX
D_D6
V-- 17 DX
R_R7
VG V++ 3.7304227e9
R_R8
V-- VG 3.7304227e9
C_C1
VG V++ 6.6667E-11
C_C2
V-- VG 6.6667E-11
*
*Mid supply Ref
E_E2 V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
E_E4 VMID V-- V++ V-- 0.5
I_ISY
V+ V- DC 0.85E-3
*
*Common Mode Gain Stage with Zero
G_G5
V++ 19 5 VMID 1
G_G6
V-- 19 5 VMID 1
G_G7
V++ VC 19 VMID 1
G_G8
V-- VC 19 VMID 1
E_EOS
12 6 VC VMID 1
L_L1
18 V++ 3.18319E-09
L_L2
20 V-- 3.18319E-09
L_L3
21 V++ 3.18319E-09
L_L4
22 V-- 3.18319E-09
R_R9
19 18 1e-3
R_R10
20 19 1e-3
R_R11
VC 21 1e-3
R_R12
22 VC 1e-3
*
*Pole Stage
G_G9
V++ 23 VG VMID 1.2566e-3
G_G10
V-- 23 VG VMID 1.2566e-3
R_R13
23 V++ 795.7981
FIGURE 65. SPICE NET LIST
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R_R14
V-- 23 795.7981
C_C3
23 V++ 10e-12
C_C4
V-- 23 10e-12
*
*Output Stage with Correction Current
Sources
G_G11
26 V-- VOUT 23 12.5e-3
G_G12
27 V-- 23 VOUT 12.5e-3
G_G13
VOUT V++ V++ 23 12.5e-3
G_G14
V-- VOUT 23 V-- 12.5e-3
D_D7
23 24 DX
D_D8
25 23 DX
D_D9
V-- 26 DY
D_D10 V++ 26 DX
D_D11
V++ 27 DX
D_D12 V-- 27 DY
V_V5
24 VOUT -0.4
V_V6
VOUT 25 -0.4
R_R15
VOUT V++ 80
R_R16
V-- VOUT 80
.model PNP_LATERAL pnp(is=1e-016
bf=250 va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model PNP_input pnp(is=1e-016 bf=100
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model DBREAK D(bv=43 rs=1)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28118_218
FN7532.7
July 27, 2015