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ISL6740_14 Datasheet, PDF (21/28 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers
ISL6740, ISL6741
Component List
REFERENCE
DESIGNATOR VALUE
DESCRIPTION
C1
1.0μF Capacitor, 1812, X7R, 100V, 20%
TDK C4532X7R2A105M
C2, C3
3.3μF Capacitor, 1812, X5R, 50V, 20%
TDK C4532X5R1H335M
C4, C6
1.0μF Capacitor, 0805, X5R, 16V, 10%
TDK C2012X5R1C105K
C5, C15, C16 0.1μF Capacitor, 0603, X7R, 50V, 10%
TDK C1608X7R1H104K
C7
Open Capacitor, 0603, Open
C8
22μF Capacitor, 1812, X5R, 16V, 20%
TDK C4532X5R1C226M
C9
150μF Capacitor, Radial, Sanyo 16SH150M
C10, C11, C12, 1000pF Capacitor, 0603, X7R, 50V, 10%
C13, C14
TDK C1608X7R1H102K
C17
220pF Capacitor, 0603, COG, 16V, 5%
TDK C1608COG1C221J
C18
0.047μF Capacitor, 0603, X7R, 16V, 10%
TDK C1608X7R1C473K
CR1, CR2
CR3
D1
L1
L2
L3
190nH
1.5μH
Short
Diode, Schottky, BAT54S
Diode, Schottky, BAT54
Zener, 10V, Philips BZX84-C10
Pulse, P2004T
Pulse, PG0077.142
Jumper or Optional Discrete Leakage
Inductance
Q5
QL, QH
QR1, QR2, QR3,
QR4
R1, R10
3.3
R2
3.01k
R3, R6
10.0
R5
3.32
R7
75.0k
R8, R9
20.0
R11
100
R12
8.06k
R13
17.4k
R14
Open
R15
1.27k
R17
97.6k
R18
3.01k
R19, RT1
10.0k
T1
T2
U1
U3
Transistor, ON MJD31C
FET, Fairchild FDS3672
FET, Fairchild FDS5670
Resistor, 2512, 5%
Resistor, 2512, 1%
Resistor, 0603, 1%
Resistor, 0603, 1%
Resistor, 0805, 1%
Resistor, 0805, 1%
Resistor, 0603, 1%
Resistor, 0603, 1%
Resistor, 0603, 1%
Resistor, 0603, Open
Resistor, 0603, 1%
Resistor, 0603, 1%
Resistor, 0603, 1%
Resistor, 0603, 1%
Midcom 31718
Pulse P8205T
Intersil HIP2101IB
ISL6740IB
Adding Line Only Regulation - Feed Forward
Output voltage variation caused by changes in the supply voltage
may be virtually removed through a technique known as feed
forward compensation. Using feed forward, the duty cycle is
directly controlled based on changes in the input voltage only. No
closed loop feedback system is required. Voltage feed forward
may be implemented as shown in Figure 18.
R109
3.48k
VREF
+VIN
R110
698
R111
806
1.5V
0.8V
R100
69.8k
R101
2k
R102
100k
R103
49.9k
R106
100K
+ U100A
-
R105
100k
R104
100k
U100B
+
-
C100
1nF
R107
100k
R108
100k
to VERROR
FIGURE 18. VOLTAGE FEED FORWARD CIRCUIT
The circuit provides feed forward compensation for a 2:1 input
voltage range. Resistors R100 and R101 set the input voltage
divider to generate a 1V signal at the input voltage that
corresponds to maximum duty cycle (VIN minimum). Resistors
R109, R110, and R111 form a voltage divider from VREF to create
reference voltages for the amplifiers. The first stage uses U100A,
R102, R103, R104, and C100 to form a unity gain inverting
amplifier. Its output varies inversely with input voltage and
ranges from 1V to 2V. The bandwidth of the circuit may be
controlled by varying the value of C100. The gain of the first
amplifier stage is:
VA = –VD + 3.00
V
(EQ. 25)
where:
VA = Output voltage of U100A
VD = The input divider voltage
The second stage uses U100B, R105, R106, R107, and R108 to
form a summing amplifier which offsets the first stage output by
0.8V (the value of CT valley voltage). The signal applied to the
VERROR input now matches the offset and amplitude of the
oscillator sawtooth so that the duty cycle varies linearly from
100% to 50% of maximum with a 2:1 input voltage variation.
21
FN9111.6
December 2, 2011