ISL6740_14 Datasheet, PDF (12/28 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, ISL6741
where t_C and t_D are the charge and discharge times, respectively,
t_SW is the oscillator free running period, and f is the oscillator
frequency. One output switching cycle requires two oscillator
cycles. The actual times will be slightly longer than calculated
due to internal propagation delays of approximately
10ns/transition. This delay ads directly to the switching duration,
but also causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very low charge
and discharge currents are used, there will be increased error
due to the input impedance at the C_T pin.
The maximum duty cycle, D, and percent deadtime, DT, can be
calculated from:
D = ---^t--^C----
t_SW
(EQ. 5)
DT = 1 – D
(EQ. 6)
Implementing Synchronization
The oscillator can be synchronized to an external clock applied to
the SYNC pin or by connecting the SYNC pins of multiple ICs
together. If an external master clock signal is used, the free
running frequency of the oscillator should be ~10% slower than
the desired synchronous frequency. The external master clock
signal should have a pulse width greater than 20ns. The SYNC
circuitry will not respond to an external signal during the first
60% of the oscillator switching cycle. Self-synchronization is not
recommended for oscillator frequencies above 900 kHz. For
higher switching frequencies, an external clock with a pulse
width less than one-half of the oscillator period must be used.
The SYNC input is edge triggered and its duration does not affect
oscillator operation. However, the deadtime is affected by the
SYNC frequency. A higher frequency signal applied to the SYNC
input will shorten the deadtime. The shortened deadtime is the
result of the timing capacitor charge cycle being prematurely
terminated by the external SYNC pulse. Consequently, the timing
capacitor is not fully charged when the discharge cycle begins.
This effect is only a concern when an external master clock is
used, or if units with different operating frequencies are
paralleled.
Soft-start Operation
The ISL6740, ISL6741 feature a soft-start using an external
capacitor in conjunction with an internal current source. soft-start
reduces stresses and surge currents during start up.
Upon start up, the soft-start circuitry clamps the error voltage
input (V_ERROR pin) indirectly to a value equal to the soft-start
voltage. The soft-start clamp does not actually clamp the error
voltage input as is done in many implementations. Rather the
PWM comparator has two inverting inputs such that the lower
voltage is in control.
The output pulse width increases as the soft-start capacitor
voltage increases. This has the effect of increasing the duty cycle
from zero to the regulation pulse width during the soft-start
period. When the soft-start voltage exceeds the error voltage,
soft-start is completed. soft-start occurs during start-up, after
recovery from a Fault condition or overcurrent/short circuit
shutdown. The soft-start voltage is clamped to 4.5V.
The Fault signal output is high impedance during the soft-start
cycle. A pull-up resistor to VREF or a pull-down resistor to ground
should be added to achieve the desired state of Fault during soft-
start.
Gate Drive
The ISL6740, ISL6741 are capable of sourcing and sinking 0.5A
peak current, but are primarily intended to be used in
conjunction with a MOSFET driver due to the 5V drive level. To
limit the peak current through the IC, an external resistor may be
placed between the totem-pole output of the IC (OUTA or OUTB
pin) and the gate of the MOSFET. This small series resistor also
damps any oscillations caused by the resonant tank of the
parasitic inductances in the traces of the board and the FET’s
input capacitance.
Undervoltage Monitor and Inhibit
The UV input is used for input source undervoltage lockout and
inhibit functions. If the node voltage falls below 1.00V a UV
shutdown fault occurs. This may be caused by low source voltage
or by intentional grounding of the pin to disable the outputs.
There is a nominal 10μA switched current source used to create
hysteresis. The current source is active only during an UV/Inhibit
fault; otherwise, it is inactive and does not affect the node
voltage. The magnitude of the hysteresis is a function of the
external resistor divider impedance. If the resistor divider
impedance results in too little hysteresis, a series resistor
between the UV pin and the divider may be used to increase the
hysteresis. A soft-start cycle begins when the UV/Inhibit fault
clears.
The voltage hysteresis created by the switched current source
and the external impedance is generally small due to the large
resistor divider ratio required to scale the input voltage down to
the UV threshold level. A small capacitor placed between the UV
input and ground may be required to filter noise out.
V_IN
R1
R3
R2
1.00V +
-
10μA
ON
FIGURE 5. UV HYSTERESIS
As V_IN decreases to a UV condition, the threshold level is:
V_IN(DOWN)
=
R_-----1_-----+-----R_----2_--
R2
V
(EQ. 7)
12
FN9111.6
December 2, 2011