ISL6740_14 Datasheet, PDF (17/28 Pages) Intersil Corporation – Flexible Double Ended Voltage and Current Mode PWM Controllers

ISL6740, ISL6741
FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING
FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR
WINDINGS
∅0.358
∅0.689
0.807
0.639
0.403
0.169
0.000
0.000 0.184
0.479
0.774 1.054
FIGURE 7G. PWB DIMENSIONS
MOSFET Selection
The criteria for selection of the primary side half-bridge FETs and
the secondary side synchronous rectifier FETs is largely based on
the current and voltage rating of the device. However, the FET
drain-source capacitance and gate charge cannot be ignored.
The zero voltage switch (ZVS) transition timing is dependent on
the transformer’s leakage inductance and the capacitance at the
node between the upper FET source and the lower FET drain. The
node capacitance is comprised of the drain-source capacitance
of the FETs and the transformer parasitic capacitance. The
leakage inductance and capacitance form an LC resonant tank
circuit which determines the duration of the transition. The
amount of energy stored in the LC tank circuit determines the
transition voltage amplitude. If the leakage inductance energy is
too low, ZVS operation is not possible and near or partial ZVS
operation occurs. As the leakage energy increases, the voltage
amplitude increases until it is clamped by the FET body diode to
ground or V_IN, depending on which FET conducts. When the
leakage energy exceeds the minimum required for ZVS
operation, the voltage is clamped until the energy is transferred.
This behavior increases the time window for ZVS operation. This
behavior is not without consequences, however. The transition
time and the period of time during which the voltage is clamped
reduces the effective duty cycle.
The gate charge affects the switching speed of the FETs. Higher
gate charge translates into higher drive requirements and/or
slower switching speeds. The energy required to drive the gates is
dissipated as heat.
The maximum input voltage, V_IN, plus transient voltage,
determines the voltage rating required. With a maximum input
voltage of 53V for this application, and if we allow a 10% adder
for transients, a voltage rating of 60V or higher will suffice.
The RMS current through the each primary side FET can be
determined from Equation 17, substituting 5A of primary current
for I_OUT. The result is 3.5A RMS. Fairchild FDS3672 FETs, rated at
100V and 7.5A (r_DS(ON) = 22mΩ), were selected for the half-
bridge switches.
The synchronous rectifier FETs must withstand approximately
one half of the input voltage assuming no switching transients
are present. This suggests a device capable of withstanding at
least 30V is required. Empirical testing in the circuit revealed
switching transients of 20V were present across the device
indicating a rating of at least 60V is required.
The RMS current rating of 7.07A for each SR FET requires a low
r_DS(ON) to minimize conduction losses, which is difficult to find in a
60V device. It was decided to use two devices in parallel to simplify
the thermal design. Two Fairchild FDS5670 devices are used in
parallel for a total of four SR FETs. The FDS5670 is rated at 60V
and 10A (r_DS(ON) = 14mΩ).
Oscillator Component Selection
The desired operating frequency of 235kHz for the converter was
established in “Design Criteria” on page 14. The oscillator
frequency operates at twice the frequency of the converter
because two clock cycles are required for a complete converter
period.
During each oscillator cycle the timing capacitor, C_T, must be
charged and discharged. Determining the required discharge
time to achieve zero voltage switching (ZVS) is the critical design
goal in selecting the timing components. The discharge time sets
the deadtime between the two outputs, and is the same as ZVS
transition time. Once the discharge time is determined, the
remainder of the period becomes the charge time.
The ZVS transition duration is determined by the transformer’s
primary leakage inductance, L_lk, by the FET Coss, by the
transformer’s parasitic winding capacitance, and by any other
parasitic elements on the node. The parameters may be
17
FN9111.6
December 2, 2011