ISL6257 Datasheet, PDF (20/22 Pages) Intersil Corporation – Highly Integrated Narrow VDC Battery Charger for Notebook Computers

ISL6257
60
F
DP
Compensator
40
Modulator
Loop
20
0
F _Z1
-20
F
FILTER
-40
-60
0.01
F
ZESR
0.1
1
10
100
FREQUENCY (kHz)
1000
FIGURE 26. CHARGE CURRENT LOOP BODE PLOTS
C_ICOMP should be chosen using Equation 31 to set
F_Z1 = F_DP/10. The crossover frequency will be approximately
2.5 * F_DP. The phase margin will be between +10°C and
+40°C depending on F_ZESR.
C_ICOMP
=
-------⁴-----^â‹---^g---^m-----²--------
2π ⋅ F_DP ⁄ 10
(EQ. 31)
Adapter Current Limit Control Loop
If the combined battery charge current and system load
current draws current that equals the adapter current limit
set by the ACLIM pin, ISL6257 will reduce the current to the
battery and/or reduce the output voltage to hold the adapter
current at the limit. Figure 17 shows the effect on output
voltage as the load current is swept up beyond the adapter
current limit. Above the adapter current limit the minimum
current buffer equals the output of gm3 and ICOMP controls
the charger output. Figure 27 shows the resulting adapter
current control system.
A filter should be added between R_S1 and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the cross over frequency and the switching
frequency (~100kHz).
DCIN
R_S1
R_F1
L
11
PHASE
C_F1
S_Σ
+
0.25
-
CSIN
CSIP
-
20
+
CA1
+
20 _-
CA2
CSOP
CSON
ICOMP
CICOMP
-
gm3
+
ACLIM +
-
C_O
R_ESR
R_F2
C_F2
RS2
RBAT
FIGURE 27. ADAPTER CURRENT LIMIT LOOP
The loop response equations, bode plots and the selection
of C_ICOMP are the same as the charge current control loop
with loop gain reduced by the duty cycle. In other words, if
the duty cycle D = 50%, the loop gain will be 6dB lower than
the loop gain in Figure 26. This gives lower crossover
frequency and higher phase margin in this mode.
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
20
FN9288.2
January 17, 2007