ISL6257 Datasheet, PDF (12/22 Pages) Intersil Corporation – Highly Integrated Narrow VDC Battery Charger for Notebook Computers

ISL6257
Theory of Operation
Introduction
The ISL6257 includes all of the functions necessary to
charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high
efficiency synchronous buck converter is used to control the
charging voltage and charging current up to 10A. The
ISL6257 has input current limiting and analog inputs for
setting the charge current and charge voltage; CHLIM inputs
are used to control charge current. VADJ and CELLS inputs
are used to control charge voltage.
The ISL6257 charges the battery with constant charge current
(set by the CHLIM input) until the battery voltage rises to a
programmed charge voltage (set by the VADJ and CELLS
input) then the charger begins to operate in a constant voltage
mode. The charger also drives an adapter isolation P-channel
MOSFET on SGATE to efficiently switch in the adapter supply.
The EN input allows shutdown of the charger through a
command from a micro-controller. It also uses EN to safely
shutdown the charger when the battery is in extremely hot
conditions. Figure 19 shows the IC functional block diagram.
The synchronous buck converter uses external N-channel
MOSFETs to convert the input voltage to the required
charging current and charging voltage. Figure 20 shows the
ISL6257 typical application circuit which uses a
micro-controller to adjust the charging current set by CHLIM
input for aircraft power applications. The voltage at CHLIM
and the value of R11 sets the charging current. The DC/DC
converter generates the control signals to drive two external
N-channel MOSFETs to regulate the voltage and current set
by the ACLIM, CHLIM, VADJ and CELLS inputs.
The ISL6257 features a voltage regulation loop (VCOMP)
and two current regulation loops (ICOMP). The VCOMP
voltage regulation loop monitors CSON to ensure that its
voltage never exceeds the battery charge voltage set by
VADJ and CELLS. The ICOMP current regulation loops
regulate the battery charging current delivered to the battery
to ensure that it never exceeds the charging current limit set
by CHLIM; and the ICOMP current regulation loops also
regulate the input current drawn from the AC adapter to
ensure that it never exceeds the input current limit set by
ACLIM, and to prevent a system crash and AC adapter
overload.
PWM Control
The ISL6257 employs a fixed frequency PWM voltage mode
control architecture with a feed-forward function. The
feed-forward function maintains a constant modulator gain of
11 to achieve fast line regulation as the buck input voltage
changes. When the battery charge voltage approaches the
input voltage, the DC/DC converter operates in dropout
mode, where there is a timer to prevent the frequency from
dropping into the audible frequency range. It can achieve
duty cycle of up to 99.6%.
An adaptive gate drive scheme is used to control the dead
time between two switches. The dead time control circuit
monitors the LGATE output and prevents the upper side
MOSFET from turning on until LGATE is fully off, preventing
cross-conduction and shoot-through. In order for the dead
time circuit to work properly, there must be a low resistance,
low inductance path from the LGATE driver to MOSFET
gate, and from the source of MOSFET to PGND. The
external Schottky diode is between the VDDP pin and BOOT
pin to keep the bootstrap capacitor charged.
Setting the Battery Regulation Voltage
The ISL6257 uses a high-accuracy trimmed band-gap
voltage reference to regulate the battery charging voltage.
The VADJ input adjusts the charger output voltage. The
VADJ control voltage can vary from 0 to VREF, providing a
10% adjustment range (from 4.2V - 5% per cell to 4.2V + 5%
per cell) on CSON regulation voltage. An overall voltage
accuracy of better than 0.5% is achieved.
The per-cell battery termination voltage is a function of the
battery chemistry. Consult the battery manufacturers to
determine this voltage.
• Float VADJ to set the battery voltage
V_CSON = 4.2V × number of the cells,
• Connect VADJ to VREF to set 4.41V × number of cells,
• Connect VADJ to ground to set 3.99V × number of the
cells.
So, the maximum battery voltage of 17.6V can be achieved.
Note that other battery charge voltages can be set by
connecting a resistor divider from VREF to ground. The resistor
divider should be sized to draw no more than 100µA from
VREF or connect a low impedance voltage source like the D/A
converter in the micro-controller. The programmed battery
voltage per cell can be determined by Equation 1:
V_CELL = 0.175 ⋅ V_VADJ + 3.99V
(EQ. 1)
An external resistor divider from VREF sets the voltage at
VADJ according to Equation 2:
V_VADJ = VREF × _R----t--_o---_p---_{_}---_V---_A---_D----_J----R_|-_|--^b-5--^o-1--^t-4-^_--k-^V---_Ω^A---^D---₊-^J----R^|-^|--_b-5--_o-1--_t-4-_{_}--k-_V---^Ω_A---_D----_J----_|-_|---5---1---4---k----_Ω--
(EQ. 2)
To minimize accuracy loss due to interaction with VADJ's
internal resistor divider, ensure the AC resistance looking
back into the external resistor divider is less than 25k.
Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+
cells. When charging other cell chemistries, use CELLS to
select an output voltage range for the charger. The internal
error amplifier gm1 maintains voltage regulation. The voltage
error amplifier is compensated at VCOMP. The component
values shown in Figure 20 provide suitable performance for
most applications. Individual compensation of the voltage
12
FN9288.2
January 17, 2007