ISL6257 Datasheet, PDF (19/22 Pages) Intersil Corporation – Highly Integrated Narrow VDC Battery Charger for Notebook Computers

ISL6257
The compensation network consists of the voltage error
amplifier gm1 and the compensation network R₁, C₁, R₂ and
C₂. R₃ and R₄ are internal divider resisters that set the DC
output voltage. For a 3 cell battery, R₃ = 320kΩ and
R₄ = 64kΩ. The equations below relate the compensation
network’s poles, zeros and gain to the components in Figure
20. Figure 24 shows an asymptotic Bode plot of the DC/DC
converter’s gain vs. frequency. It is strongly recommended
that F_Z1 is approximately 1/4*F_DP and F_Z2 is approximately
1/2*F_DP.
60
Loop
50
Modulator
40
Compensator
F_DP
30
20
10
F P1
0
-10
F_Z1
-20
-30
-40
0.01
F
Z2
F
ZESR
0.1
1
10
100
FREQUENCY (kHz)
1000
FIGURE 24. ASYMPTOTIC BODE PLOT OF THE VOLTAGE
CONTROL LOOP GAIN
Compensation Break Frequency Equations
F_Z1 = ₍---₂---_π-----_â‹---_C----₁-----_â‹--¹-₍--_R----₁----+-----_R----₃---₎---₎
(EQ. 23)
F_Z2
=
----------------------------¹------------------------------
⎛
⎜2π
⎝
⋅
C₂
⋅
⎧
⎩⎨ ^{R 2}
–
-----¹-----
gm1
⎫⎞
⎬⎟
⎭⎠
-----¹-----
gm1
=
4.17 k Ω
(EQ. 24)
F_DP
=
---------------¹---------------
(2π L ⋅ C_o)
F_ESR
=
--------------------¹--------------------
(2π ⋅ C_o ⋅ R_ESR)
F_P1 = ₍---₂---_π-----_â‹---_R--¹--₁----_â‹---_C-----₁---₎
(EQ. 25)
(EQ. 26)
TABLE 3.
CELLS
2
R₃
288kΩ
3
320kΩ
4
336kΩ
Charge Current Control Loop
When the battery voltage is less than the fully charged
voltage, the voltage error amplifier goes to it’s maximum
output (limited to 1.2V above ICOMP) and the ICOMP
voltage controls the loop through the minimum voltage
buffer. Figure 25 shows the charge current control loop.
11
PHASE
L
C_O
R_ESR
Σ^S
ICOMP
C_ICOMP
+
0.25
-
-
gm2
+
+
20 _-
CA2
CSOP
CSON
CHLIM
+
-
R_F2
C_F2
R_S2
R_BAT
FIGURE 25. CHARGE CURRENT LIMIT LOOP
The compensation capacitor (C_ICOMP) gives the error
amplifier (gm2) a pole at a very low frequency (<<1Hz) and a
a zero at F_Z1. F_Z1 is created by the 0.25*CA2 output added to
ICOMP. The loop response has another zero due to the
output capacitor’s esr.
A filter should be added between R_S2 and CSOP and CSON
to reduce switching noise. The filter roll off frequency should
be between the cross over frequency and the switching
frequency (~100kHz). R_F2 should be small (<10Ω) to
minimize offsets due to leakage current into CSOP.
F_DP
=
---------------¹---------------
(2π L ⋅ C_o)
(EQ. 27)
F_ZESR
=
--------------------¹--------------------
(2π ⋅ C_o ⋅ R_ESR)
(EQ. 28)
F_Z1
=
----------⁴-----^â‹---^g---^m-----²-----------
(2π ⋅ C_ICOMP)
gm2 = 50μA ⁄ V
F_FILTER
=
--------------------¹--------------------
(2π ⋅ C_F2 ⋅ R_F2)
(EQ. 29)
(EQ. 30)
19
FN9288.2
January 17, 2007