ISL78233 Datasheet, PDF (2/18 Pages) Intersil Corporation – 3A and 4A Compact Synchronous Buck Regulators

ISL78233, ISL78234
ISL78233, ISL78234
(16 LD TQFN)
TOP VIEW
16
15
14
13
VIN 1
VDD 2
PG 3
SYNC 4
12 PGND
11 PGND
10 SGND
9 FB
5
6
7
8
Pin Descriptions
PIN NUMBER
1, 16
SYMBOL
VIN
2
VDD
3
PG
4
SYNC
5
EN
6
FS
7
SS
8, 9
COMP, FB
10
11, 12
13, 14, 15
Exposed Pad
SGND
PGND
PHASE
-
DESCRIPTION
Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as
possible to the IC for decoupling.
Input supply voltage for the logic. Connect to VIN pin.
Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNC pin float.
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low.
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 2MHz
if FS is connected to VIN.
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, FB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if COMP not tied to VDD. Otherwise, COMP is
disconnected thru a MOSFET for internal compensation. Must connect COMP to VDD in internal
compensation mode. The output voltage is set by an external resistor divider connected to FB. With a
properly selected divider, the output voltage can be set to any voltage between the power rail (reduced
by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical
application. Additional external networks across COMP and SGND might be required to improve the
loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the
regulator output voltage.
Signal ground
Power ground
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω
resistor when the device is disabled. See “Functional Block Diagram” on page 4 for more detail.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
many vias as possible under the pad connecting to SGND plane for optimal thermal performance.
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FN8359.5
April 23, 2015