ISL78233 Datasheet, PDF (15/18 Pages) Intersil Corporation – 3A and 4A Compact Synchronous Buck Regulators

ISL78233, ISL78234
^iin
V^in
+
^iL _LP
R_LP
ILd^ 1:D ^{Vind^}
RT
vo^
Rc
Ro
Co
d^
T _i(S)
K
Fm
+
He(S)
Tv(S)
v^comp _-Av(S)
FIGURE 35. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Vo
R₂
C₃
VFB _-
R₃
VREF
GM
+
VCOMP
R₆
C₇
C₆
FIGURE 36. TYPE II COMPENSATOR
Figure 36 shows the type II compensator and its transfer function
is expressed as Equation 5:
A_vS= -^vˆ---c_v-ˆ--^oF---^m-_B----^p- = -_--_C-----₆----+-----_C-^G---₇--^M--_---_--^-_--^R-_R---³-₂-----+-----_R----₃----_ -_S--^--_-¹--₁---+--+---^----_{--------}^cS------_cS---^z------_p---¹-----₁--^--_-^--_-¹--₁---+--+----^----_{-------}^c-^S-----_c--_S-^z------_p---²------_2-^---_-_{(EQ. 5)}
Where,
_cz1 = -_R----₆--¹-_C-----₆- ,
_cz2 = -_R----₂--¹-_C-----₃- _cp1= _R--^C---₆-⁶--_C---+--₆--^C-_C----⁷-₇- _cp2= _C--^R---₃-²--_R---+--₂--^R-_R----³-₃-
Compensator design goal:
High DC gain
Choose Loop bandwidth f_c less than 100kHz
Gain margin: >10dB
Phase margin: >40°
The compensator design procedure is as follows:
The loop gain at crossover frequency of f_c has a unity gain.
Therefore, the compensator resistance R₆ is determined by
Equation 6.
R₆ = -²---^-_G---^f--_M^c---^V---_-^o--_V--^C--_F--^o--_B--^R----^t = 17.4510³  f_cV_oC_o
(EQ. 6)
Where GM is the sum of the trans-conductance, g_m, of the
voltage error amplifier in each phase. Compensator capacitor C₆
is then given by Equation 7.
C₆ = ^R-----_R^o---^C-₆----^o- = -^V-_I--_o-^o--_R-^C---₆--^o- ,C₇= max(^R----_R-^c---^C-₆----^o-,_----_f--_s-¹--_R-----₆-)
(EQ. 7)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 7. An optional zero can boost the phase margin. _CZ2 is
a zero due to R₂ and C₃
Put compensator zero 2 to 5 times f_c:
C₃= _----_f--_c-¹--_R-----₂-
(EQ. 8)
Example: V_IN = 5V, V_O = 1.8V, I_O = 4A, FS = 1MHz, R₂ = 200kΩ,
R₃ = 100kΩ, C_o = 2x22µF/3mΩ, L = 1µH, f_c = 100kHz, then
compensator resistance R₆:
R₆ = 17.4510³  100kHz  1.8V  44F = 138k
(EQ. 9)
It is acceptable to use 137kΩas theclosest standard value for
R₆.
C₆ = ¹-₄---^.-_A-⁸---^V-_---₁--^--₃-⁴--₇-⁴---_k-^--_--^F-- = 144pF
(EQ. 10)
C₇= max(-³---^m----₁--^-₃---₇--^--_k-⁴---_⁴----^----^F--,-_----_---₁----_M------_H----_z-¹---_--₁----₃---₇----_k---_------_)= (1pF,2.3pF) (EQ. 11)
It is also acceptable to use the closest standard values for C₆ and
C₇. There is approximately 3pF parasitic capacitance from V_COMP
to GND; Therefore, C₇ is optional. Use C₆ = 150pF and C₇ = OPEN.
C₃= _----₁----₀---₀----_k---_H-----_z1-----_---₂---₀---₀----_k----_-- = 16pF
(EQ. 12)
Use C₃ = 15pF. Note that C₃ may increase the loop bandwidth
from previous estimated value. Figure 37 on page 16 shows the
simulated voltage loop gain. It is shown that it has a 150kHz loop
bandwidth with a 42° phase margin and 10dB gain margin. It
may be more desirable to achieve an increased phase margin.
This can be accomplished by lowering R₆ by 20% to 30%.
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FN8359.5
April 23, 2015