ISL78233 Datasheet, PDF (13/18 Pages) Intersil Corporation – 3A and 4A Compact Synchronous Buck Regulators

ISL78233, ISL78234
PWM
PFM
PWM
CLOCK
I_L
0
16 CYCLES
NOMINAL +1%
PFM CURRENT LIMIT
LOAD CURRENT
V_OUT
NOMINAL
NOMINAL -1.5%
FIGURE 34. SKIP MODE OPERATION WAVEFORMS
Frequency Adjust
The frequency of operation is fixed at 2MHz when FS is tied to VIN.
Adjustable frequency ranges from 500kHz to 4MHz via a simple
resistor connecting FS to SGND according to Equation 1:
R_FSk = -_f-_O--²---_S²---⁰-_C----_---_k1---_H0----³-_z----_ – 14
(EQ. 1)
The ISL78233, ISL78234 also has frequency synchronization
capability by simply connecting the SYNC pin to an external
square pulse waveform. The frequency synchronization feature
will synchronize the positive edge trigger and its switching
frequency up to 4MHz. The minimum external SYNC frequency is
half of the free running frequency (either the default frequency or
determined by the FS resistor).
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 4.
The current sensing circuit has a gain of 200mV/A, from the P-FET
current to the CSA output. When the CSA output reaches the
threshold, the OCP comparator is tripled to turn off the P-FET
immediately. The overcurrent function protects the switching
converter from a shorted output by monitoring the current flowing
through the upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the regulator will be shut down
under an overcurrent fault condition. An overcurrent fault
condition will result in the regulator attempting to restart in a
hiccup mode within the delay of eight soft-start periods. At the
end of the 8th soft-start wait period, the fault counters are reset
and soft-start is attempted again. If the overcurrent condition
goes away during the delay of 8 soft-start periods, the output will
resume back into regulation point after hiccup mode expires.
Negative Current Protection
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side N-FET, as shown in
Figure 3 on page 4. When the valley point of the inductor current
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reaches -3A for 4 consecutive cycles, both P-FET and N-FET are off.
The 100Ω in parallel to the N-FET will activate discharging the
output into regulation. The control will begin to switch when output
is within regulation. The regulator will be in PFM for 20µs before
switching to PWM if necessary.
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When VFB drops 15% below
or raises 0.8V above the nominal regulation voltage, the ISL78233,
ISL78234 pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
output voltages, connect an external pull-up resistor, R₁, between
PG and VIN. A 100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
Soft Start-up
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed, so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz, so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the SKIP mode to
support prebiased output condition.
Tie SS to SGND for internal soft-start is approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 2.1µA current source
sets the soft-start interval of the converter, t_SS as shown by
Equation 2.
C_SSF = 3.1  t_SSs
(EQ. 2)
C_SS must be less than 33nF to insure proper soft-start reset after
fault condition.
FN8359.5
April 23, 2015