ISL78215 Datasheet, PDF (2/11 Pages) Intersil Corporation – Improved Industry Standard Single-Ended Current Mode PWM Controller

ISL78215
Pin Description
PIN
1
SYMBOL
COMP
2
FB
3
CS
4
RTCT
DESCRIPTION
COMP is the output of the error amplifier and the input of the PWM comparator. The
control loop frequency compensation network is connected between the COMP and FB
pins.
The output voltage feedback is connected to the inverting input of the error amplifier
through this pin. The non-inverting input of the error amplifier is internally tied to a
reference voltage.
This is the current sense input to the PWM comparator. The range of the input signal is
nominally 0V to 1.0V and has an internal offset of 100mV.
This is the oscillator timing control pin. The operational frequency and maximum duty
cycle are set by connecting a resistor, RT, between VREF and this pin and a timing
capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a
programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time,
tD, the switching frequency, f, and the maximum duty cycle, Dmax, can be calculated
from Equations 1, 2, 3 and 4:
tC ≈ 0.583 • RT • CT
(EQ. 1)
t
D
≈
–R
T
•
CT
•
ln
⎛
⎝
00_----.._-00_----00_---88_---33_-----••_-----RR_----TT_{------––----}42_---.._--34_{--⎠⎞}
(EQ. 2)
f = 1 ⁄ (tC + tD)
(EQ. 3)
D = tC • f
(EQ. 4)
Figure 4 may be used as a guideline in selecting the capacitor and resistor values required
for a given frequency.
5
GND
GND is the power and small signal reference ground for all functions.
6
OUT
This is the drive output to the power switching device. It is a high current output capable
of driving the gate of a power MOSFET with peak currents of 1.0A.
7
VDD
VDD is the power connection for the device. The total supply current will depend on the
load applied to OUT. Total IDD current is the sum of the operating current and the
average output current. Knowing the operating frequency, f, and the MOSFET gate
charge, Qg, the average output current can be calculated in Equation 5:
I_OUT = Qg × f
(EQ. 5)
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the
VDD and GND pins as possible.
8
VREF
The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating
temperature. Bypass to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Ordering Information
PART NUMBER
(Notes 2, 3)
PART MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL78215AUZ
78215
-40 to +105
8 Ld MSOP
M8.118
ISL78215AUZ-T (Note 1)
78215
-40 to +105
8 Ld MSOP
M8.118
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78215. For more information on MSL please
see techbrief TB363.
2
FN7673.0
August 16, 2010