ISL6121 Datasheet, PDF (2/16 Pages) Intersil Corporation – Single Supply Integrated Current Limiting Controller

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128
AIN
BIN
CIN
DIN
AOUT
BOUT
COUT
DOUT
V_DD
ENABLE
SYSRST#
RESET#
GROUND
UVLO_A
UVLO_B
UVLO_C
UVLO_D
Pinout
ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128 (QFN)
TOP VIEW
24 23 22 21 20 19
1
18
2
17
3
16
4
15
5
14
6
7
13
8 9 10 11 12
4mm X 4mm
FIGURE 1. TYPICAL ISL6123 APPLICATION USAGE
Pin Descriptions
PIN # PIN NAME
FUNCTION
DESCRIPTION
23
VDD
Chip Bias
Bias IC from nominal 1.5V to 5V
10
GND
Bias Return
IC ground
1 ENABLE_1/ Input to start on/off Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is
ENABLE#_1 sequencing.
disabled for 10ms after UVLO is satisfied. ISL6123 has ENABLE. ISL6124, ISL6125, ISL6126 and
11 ENABLE#_2
ISL6127 have ENABLE#. Only ISL6128 has 2 ENABLE# inputs, 1 for each 2 channel grouping.
EN_1# for (A, B), and EN_2# for (C, D).
24 RESET# RESET# Output
9 RESET#_2
RESET# provides a low signal 150ms after all GATEs are fully enhanced. This delay is for stabilization of
output voltages. RESET# will assert low upon UVLO not being satisfied or ENABLE/ENABLE# being
deasserted. The RESET outputs are open drain N channel FET and is guaranteed to be in the correct state
for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X.
RESET#_2 only exists on ISL6128 for (C, D) group I/O.
20 UVLO_A Under Voltage Lock These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference and
Out/Monitoring
12
UVLO_B _Input
are filtered to ignore short (<30µs) transients below programmed UVLO level.
17 UVLO_C
14 UVLO_D
21 DLY_ON_A Gate On Delay
Timer Output
8 DLY_ON_B
16 DLY_ON_C
Allows for programming the delay and sequence for Vout turn-on using a capacitor to ground. Each
cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current
source providing delay to the associated FETs GATE turn-on.
These pins are NC on ISL6126 and ISL6127
15 DLY_ON_D
18 DLY_OFF_A Gate Off Delay
Timer Output
13 DLY_OFF_B
3 DLY_OFF_C
Allows for programming the delay and sequence for Vout turn-off through ENABLE/ENABLE# via a
capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down turning-off the FET.
These pins are NC on ISL6127
4 DLY_OFF_D
2
FN9005.4
June 10, 2005