ISL6121 Datasheet, PDF (14/16 Pages) Intersil Corporation – Single Supply Integrated Current Limiting Controller

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128
prevent the turn-on sequence from completing if there is one
unsatisfied UVLO input in a group. Using this configuration
involves waiting through the T_UVLOdel and T_RSTdel (total of
~160ms) for each sequencer IC in the chain for the final
RESET# to release. Once ENABLE on the first sequencer is
deasserted all the RESET# outputs will quickly pull low and
thus allow the sequenced turn-off of this configuration to
ripple through several banks as quickly as the user
programmed sequence as chosen by the DLY_OFF
capacitors allow. Once again with common bussed
SYSRTS# pins, simultaneous shut down of all GATEs and
LOGIC down upon an unsatisfied UVLO input is assured
once all FETs or LOGIC output are on.
It is suggested that this circuit implementation be prototyped
and evaluated for the particular expected loads prior to
committing to manufacturing build.
OE
LOW= RESET
ENABLE
SYSRST#
ISL6124
#N
G
UVLO
A
T
ENABLE# E
RESET#
FIGURE 20. OUTPUT VOLTAGE ON LOW TO HIGH TRACKING
POWER
SUPPLY
ENABLE#
SYSRST#
ISL6125 _L
# N+1 _O
RESET#
G
I
UVLO
C
RESET#
RESET#
FIGURE 19. MULTIPLE ISL612X SERIAL CONFIGURATION
Voltage Tracking
In some applications the various voltages may have to track
each other as they ramp up & down whereas others may just
need sequencing. In these cases tracking can be
accomplished and has been demonstrated over a wide
range of load current (1A to 10A) and load capacitance
(10µF to 3300µF) with the ISL612X family. Figures 20 and
21 illustrate output voltage ramping tracking performance,
note that differences are less than 0.5V. With the relevant
GATE pins tied together in a star pattern, so that the
resistance between any two GATE pins is equivalent (1K to
10K) results in a sharing of the GATE ramping voltage and
with the same or similar enough FETs this behavior is
observed.
14
FIGURE 21. OUTPUT VOLTAGE HIGH TO LOW TRACKING
Negative Voltage Sequencing
They ISL612X family can use the charged pump GATE
output to drive FETs that would control and sequence
negative voltages down to a nominal -5V with minimal
additional external circuitry. Figure 22 shows turn-on of 5V
bipolar supplies together then the +2.5V and turn-off of both
positive supplies being turned off together after the -5V.
Figure 23 shows the minimal additional external circuitry to
accomplish this. The 5V zener diode is used to level shift the
GATE drive down 5V to prevent premature turn-on when
GATE = 0V. Once GATE drive voltage > Vz then FET Vgs >
5V ensuring full turn-on once GATE gets to VDD+5.3V. Turn-
on and turn-off ramp rate can be adjusted with FET gate
series resistor value. Sequencing of the -V rail is
accomplished as normal via the DLY_X capacitor value
although adjustments in prototyping should be factored in to
fine tune for actual circuit requirements.
FN9005.4
June 10, 2005