ISL6121 Datasheet, PDF (15/16 Pages) Intersil Corporation – Single Supply Integrated Current Limiting Controller

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128
Figures 24 and 25 illustrate a high accuracy -V detection
circuit using the ISL6131and a low cost low accuracy -V
detect circuit and respectively.
Application Considerations
Timing Error Sources
In any system there are variance contributors, for the ISL612X
family the timing errors are mainly contributed by three sources.
Capacitor Timing Mismatch Error
Obviously, the absolute capacitor value is an error source
thus lower percentage tolerance capacitors help to reduce
this error source. Figure 26 illustrates a difference of 0.57ms
between two DLY_X outputs ramping to DLY_X threshold
voltage, these 5% capacitors were from a common source.
In applications where two or more GATEs or LOGIC outputs
must have concurrent transitions, it is recommended that a
common DLY_X cap. be used to eliminate this timing error.
FIGURE 22. ±VOLTAGE SEQUENCING
-Vin
-Vout
R1
ISL612X GATE
D1
Additional 2 components
necessary for -V control
and sequencing.
D1 necessary to prevent premature turn-on. R1 is used
to hold FET Vgs = 0V until D1 Vz is overcome. R1 value
can be changed to adjust -V ramp rates. Choose a R1
value between 4MΩ and 10MΩ initially and fine tune
resistor value for the particular need.
FIGURE 23. -VOLTAGE FET DRIVE CIRCUIT
+V
R1
+BIAS
R3
(1K)
ISL6131
VMON
OR
R2
ISL6536A _PGOOD R4
(15K)
-BIAS
-V
R5
(10K)
Q1 Si1300DL
OR EQUIV.
TO UVLO OF
ISL612X FOR
R6 ^{-V CONTROL AND}
SEQUENCING
R1 and R2 define -V UVLO level
R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up
R4 and R5 provide Q1 gate bias between 0V and +V
to 0V (resistor values suitable for -V = -5V and +V = +3.3V)
FIGURE 24. HGH ACCURACY -V LOCK OUT
+V
R1
TO UVLO OF ISL612X FOR CONTROL
AND SEQUENCING OF -V
R2
-V
Chose R1 and R2 values to drive UVLO
high when -V is sufficiently present
FIGURE 25. LOW ACCURACY -V PRESENCE DETECTION
15
FIGURE 26. CAPACITOR TIMING MISMATCH
DLY_X Threshold Voltage and Charging Current
Mismatch
The two other error sources come from the IC itself and are
the differences in the DLY_X threshold voltage, (DLY_Vth)
when the GATE charging latch is set and the DLY_X
charging current, (DLY_ichg) across the four individual I/Os.
Both of these parameters are bounded by specification and
Figure 27 illustrates that with a common capacitor the typical
error contributed by these factors is insignificant as both
DLY_X traces overlay each other.
FIGURE 27. DLY_VTH AND DLY_ICHG TIMING MISMATCH
FN9005.4
June 10, 2005