ISL23428 Datasheet, PDF (2/21 Pages) Intersil Corporation – Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

Block Diagram
V_LOGIC
SCK
SDI
SDO
CS
SPI
INTERFACE
ISL23428
V_CC
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
RH0
RH1
WR0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
GND
Pin Configurations
ISL23428
(14 LD TSSOP)
TOP VIEW
GND 1
V_LOGIC 2
SDO 3
SCK 4
SDI 5
CS 6
GND 7
14 V_CC
13 RL0
12 RW0
11 RH0
10 RH1
9 RW1
8 RL1
ISL23428
(16 LD UTQFN)
TOP VIEW
SDO 1
SCK 2
SDI 3
CS 4
12 RW0
11 RH0
10 RH1
9 RW1
RW0 RL0
RW1 RL1
Pin Descriptions
TSSOP
1, 7
2
UTQFN
5, 6, 15
16
3
1
4
2
5
3
6
4
8
8
9
9
10
10
11
11
12
12
13
13
14
14
7
SYMBOL
DESCRIPTION
GND Ground pin
V_LOGIC SPI bus/logic supply
Range 1.2V to 5.5V
SDO Logic Pin - Serial bus data output
(configurable)
SCK Logic Pin - Serial bus clock input
SDI Logic Pin - Serial bus data input
CS Logic Pin - Active low chip select
RL1 DCP1 “low” terminal
RW1 DCP1 wiper terminal
RH1 DCP1 “high” terminal
RH0 DCP0 “high” terminal
RW0 DCP0 wiper terminal
RL0 DCP0 “low” terminal
V_CC Analog power supply.
Range 1.7V to 5.5V
NC Not Connected
2
FN7904.0
August 25, 2011