ISL23428 Datasheet, PDF (16/21 Pages) Intersil Corporation – Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23428
CS
SCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SDI
SDO
WR INSTRUCTION
ADDR
DATA BYTE
FIGURE 27. TWO BYTE WRITE SEQUENCE
CS
SCK
SDI
SDO
1
8
RD
ADDR
16
24
32
NOP
RD
ADDR
READ DATA
FIGURE 28. FOUR BYTE READ SEQUENCE
Write Operation
A write operation to the ISL23428 is a two or more bytes
operation. First, It requires the CS transition from HIGH-to-LOW.
Then the host sends a valid Instruction Byte, followed by one or
more Data Bytes to the SDI pin. The host terminates the write
operation by pulling the CS pin from LOW-to-HIGH. Instruction is
executed on the rising edge of CS (see Figure 27).
Read Operation
A Read operation to the ISL23428 is a four byte operation. First,
It requires the CS transition from HIGH-to-LOW. Then the host
sends a valid Instruction Byte, followed by a “dummy” Data Byte,
NOP Instruction Byte and another “dummy” Data Byte to SDI pin.
The SPI host receives the Instruction Byte (instruction code +
register address) and requested Data Byte from SDO pin on the
rising edge of SCK during third and fourth bytes, respectively. The
host terminates the read by pulling the CS pin from LOW-to-HIGH
(see Figure 28).
16
FN7904.0
August 25, 2011