82C88_05 Datasheet, PDF (2/11 Pages) Intersil Corporation – CMOS Bus Controller

Functional Diagram
S0
S1
S2
CONTROL
INPUT
CLK
AEN
CEN
IOB
STATUS
DECODER
CONTROL
LOGIC
82C88
COMMAND
SIGNAL
GENERATOR
CONTROL
SIGNAL
GENERATOR
MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA
DT/R
DEN
MCE/PDEN
ALE
MULTIBUS^TM
COMMAND
SIGNALS
ADDRESS LATCH,
DATA TRANSCEIVER,
AND INTERRUPT
CONTROL SIGNALS
V_CC
GND
Pin Description
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
V_CC
20
GND
10
V_CC: The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling.
GROUND.
S0, S1, S2 19, 3, 18
I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The
82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins
are not in use (passive), command outputs are held HIGH (See Table1).
CLK
2
I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
ALE
5
O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is
active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent
D type latches, such as the 82C82 and 82C83H.
DEN
16
O DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This
signal is active HIGH.
DT/R
4
O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH
on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory).
AEN
6
I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns
maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output
drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH).
CEN
15
I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control
outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
IOB
1
I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode.
When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections).
AIOWC
12
O ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to
give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal.
AIOWC is active LOW.
IOWC
11
O I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The signal
is active LOW.
IORC
13
O I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal
is active LOW.
2
FN2979.2
August 25, 2005