5962F-9568901VXC Datasheet, PDF (2/4 Pages) Intersil Corporation – Radiation Hardened Quad Differential Line Receiver

Logic Diagram
HS-26C32RH, HS-26C32EH
ENABLE ENABLE DIN DIN
CIN CIN
BIN BIN AIN AIN
+-
+-
+-
+-
DOUT
COUT
BOUT
AOUT
Pin Configurations
HS1-26C32RH, HS1-26C32EH
(16 LD SBDIP)
MIL-STD-1835: CDIP2-T16
TOP VIEW
AIN 1
AIN 2
AOUT 3
ENABLE 4
COUT 5
CIN 6
CIN 7
GND 8
16 VDD
15 BIN
14 BIN
13 BOUT
12 ENABLE
11 DOUT
10 DIN
9 DIN
Propagation Delay Timing
Diagram
-V_IN
+V_IN = 0V
V_OH
V_OL
INPUT
t_PLH
V_S = 50%
0V
t_PHL
OUTPUT
+2.5V
-2.5V
AIN
AIN
AOUT
ENABLE
COUT
CIN
CIN
GND
HS9-26C32RH, HS9-26C32EH
(16 LD FLATPACK)
MIL-STD-1835: CDFP4-F16
TOP VIEW
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VDD
BIN
BIN
BOUT
ENABLE
DOUT
DIN
DIN
Three-State Low Timing Diagram
V_IH
V_SS
V_OZ
V_OL
V_S
INPUT
t_PZL
V_T
t_PLZ
OUTPUT
V_W
2
FN3402.5
May 28, 2013