ISL6722A Datasheet, PDF (19/24 Pages) Intersil Corporation – Flexible Single Ended Current Mode PWM

ISL6722A, ISL6723A
A Bode plot of the closed loop system at low line, max load
appears below.
50
40
30
20
10
0
-10
-20
-30
-40
-50
0.01
0.1
1
10
100
FREQUENCY (kHz)
FIGURE 12A. GAIN
200
150
100
50
0
50
100
0.01
0.1
1
10
100
FREQUENCY (kHz)
FIGURE 12B. PHASE MARGIN
Regulation Performance
TABLE 1. OUTPUT LOAD REGULATION, V_IN = 48V
I_OUT (A), 3.3V I_OUT (A), 1.8V V_OUT (V), 3.3V V_OUT (V), 1.8V
0
0.030
3.351
1.825
0.39
0.030
3.281
1.956
0.88
0.030
3.251
1.988
1.38
0.030
3.223
2.014
1.87
0.030
3.204
2.029
2.39
0.030
3.185
2.057
2.89
0030
3.168
2.084
3.37
0.030
3.153
2.103
0
0.52
3.471
1.497
0.39
0.52
3.283
1.800
0.88
0.52
3.254
1.836
1.38
0.52
3.233
1.848
1.87
0.52
3.218
1.855
2.39
0.52
3.203
1.859
2.89
0.52
3.191
1.862
0
1.05
3.619
1.347
0.39
1.05
3.290
1.730
0.88
1.05
3.254
1.785
1.38
1.05
3.235
1.805
1.87
1.05
3.220
1.814
2.39
1.05
3.207
1.820
0
1.55
3.699
1.265
0.39
1.55
3.306
1.682
0.88
1.55
3.260
1.750
1.38
1.55
3.239
1.776
1.87
1.55
3.224
1.789
0
2.07
3.762
1.201
0.39
2.07
3.329
1.645
0.88
2.07
3.270
1.722
1.38
2.07
3.245
1.752
0
2.62
3.819
1.142
0.39
2.62
3.355
1.612
0.88
2.62
3.282
1.697
0
3.14
3.869
1.091
.39
3.14
3.383
1.581
19
FN9237.1
July 11, 2007