ISL6722A Datasheet, PDF (11/24 Pages) Intersil Corporation – Flexible Single Ended Current Mode PWM

ISL6722A, ISL6723A
The minimum amount of slope compensation required
corresponds to 1/2 the inductor downslope. However, adding
excessive slope compensation results in a control loop that
behaves more as a voltage mode controller than as current
mode controller.
DODWowNnSslLoOpePE
CUCRuRrrEenNtTSeSnEsNe SiEgnSaIlGNAL
TIM_TimE _e
FIGURE 5.
The minimum amount of capacitance to place at the SLOPE
pin is:
Cslope
=
4.24
×10^–6
•
------^t--^O----^N--------
Vslope
F
(EQ. 6)
where t_ON is the On time and Vslope is the amount of
voltage to be added as slope compensation to the current
feedback signal. In general, the amount of slope
compensation added is 2 to 3 times the minimum required.
Example:
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
Switching Frequency, f_sw = 250kHz
Duty Cycle, D = 60%
t_ON = D/f_sw = 0.6/250E3 = 2.4µs
t_OFF = (1 - D)/f_sw = 1.6µs
Determine the downslope:
Downslope = 0.125V/1.6µs = 78mV/µs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
Vslope
=
1_--
2
•
0.078
•
2.4
=
94 m V
(EQ. 7)
Therefore,
Cslope(min)
=
4.24
×10^–6
•
2_----._--4_---×_----1---0---^–_--⁶_--
0.094
≈ 110pF
(EQ. 8)
The value calculated, 110pF, represents the minimum slope
compensation required. An appropriate slope compensation
capacitance for this example would be 1/2 to 1/3 the
calculated value, or between 68pF and 33pF.
A more rigorous treatment of slope compensation can be
obtained from the small signal current-mode model [1]. It can
be shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is Equation 9:
Fm
=
---------¹-----------
Sn ⋅ t_sw
(EQ. 9)
where Sn is the slope of the sawtooth signal and t_sw is the
switching frequency. When an external ramp is added, the
modulator gain becomes Equation 10:
Fm
=
-----------------¹------------------
(Sn + Se)t_sw
=
------------¹------------
m_cSnt_sw
(EQ. 10)
where Se is slope of the external ramp.
m_c
=
1
+
S_-----e_--
Sn
(EQ. 11)
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, under-damped for Q > 1,
and over-damped for Q < 1. An under-damped condition
may result in current loop instability.
Q = -_π---₍---_m-----_c---₍--₁-----–--¹---_D-----₎---–-----₀---_.--₅----₎
(EQ. 12)
where D is the maximum duty cycle. Setting Q = 1 and
solving for S_e yields:
S_e
=
S_n
⎛⎛
⎝⎝
1_--
π
+
0.5_⎠⎞
------¹-------
1–D
–
1_⎠⎞
(EQ. 13)
Since S_n and S_e are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by t_ON to obtain the voltage change that occurs during t_ON.
V_e
=
V_n
⎛⎛
⎝⎝
1_-π-
+
0.5_⎠⎞
------¹-------
1–D
–
1_⎠⎞
(EQ. 14)
where V_n is the change in the current feedback signal during
the on time and V_e is the voltage that must be added by the
external ramp.
For buck-derived topologies, V_n can be solved for in terms of
output voltage, current transducer components, and output
inductance yielding:
V_e
=
t_{--S----W-------}⋅_---V_----O------⋅_---R_----C----S--
N_CT ⋅ L_O
⋅
-^N----^S--
N_P
⎛
⎝
1_π--
+
D
–
0.5_⎠⎞
V
(EQ. 15)
where R_CS is the current sense burden resistor, N_CT is the
current transformer turns ratio, L_O is the output inductance,
V_O is the output voltage, and N_s and N_p are the secondary
and primary turns, respectively.
11
FN9237.1
July 11, 2007