ISL6327A Datasheet, PDF (19/29 Pages) Intersil Corporation – Enhanced 6-Phase PWM Controller with 8-Bit VID Code and Differential Inductor DCR or Resistor Current Sensing

ISL6327A
Soft-Start
The soft-start sequence of an ISL6327A based VR is
comprised of 3 segments, as shown in Figure 8. Once VCC,
EN_VTT and EN_PWR all reach their POR/enable
thresholds, the controller initiates a fixed wait period, t_D1.
Following t_D1, the VR initiates the soft-start ramp, raising the
internal reference to the VID setpoint over the time interval,
t_D2.
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
VR_RDY
UV
50%
VOUT, 500mV/DIV
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC
+
85µA
I_AVG
tD1
t_D2
t_D3
EN_VTT
VR_RDY
500µs/DIV
FIGURE 8. SOFT-START WAVEFORMS
t_D1 is a fixed delay with the typical value as 1.36ms. During
t_D2, ISL6327A digitally controls the DAC voltage change at
6.25mV per step. The time for each step is determined by
the frequency of the soft-start oscillator which is defined by
the resistor R_SS from SS pin to GND. The soft-start ramp
time t_D2 can be calculated based on Equations 14:
t_D2
=
-1---.--1---x----R----^S----^S--
6.25 x 25
(
μ
s
)
(EQ. 14)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the soft-start ramp time t_D2 will be 704µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t_D3. The
typical value for t_D3 is 85µs.
Fault Monitoring and Protection
The ISL6327A actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to external
system monitors. The schematic in Figure 9 outlines the
interaction between the fault monitors and the VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fix delay time, t_D3. VR_RDY will be pulled low when an
undervoltage, overvoltage, or overcurrent condition is
VDIFF
+
OV
-
VID + 0.175V
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID voltage.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY gets pulled low. When the output
voltage comes back to 60% of the VID voltage, VR_RDY will
return back to high.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6327A
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before
the 2nd soft-start, the OVP threshold is 1.275V. Once the
controller detects a valid VID input, the OVP trip point will be
changed to the VID voltage plus 175mV.
Two actions are taken by the ISL6327A to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns). This causes
the Intersil drivers to turn on the lower MOSFETs and pull
the output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC plus 75mV,
PWM signals enter a high-impedance state. The Intersil
drivers respond to the high-impedance input by turning off
both upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6327A will again command the lower
MOSFETs to turn on. The ISL6327A will continue to protect
the load in this fashion as long as the overvoltage condition
occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6327A is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the POR
19
FN6833.0
February 17, 2009