ISL6327A Datasheet, PDF (13/29 Pages) Intersil Corporation – Enhanced 6-Phase PWM Controller with 8-Bit VID Code and Differential Inductor DCR or Resistor Current Sensing

ISL6327A
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6327A to include the combined tolerances of each of
these elements.
The output of the error amplifier, V_COMP, is compared to the
sawtooth waveforms to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitries, which control the
voltage regulation, are illustrated in Figure 5.
The ISL6327A incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground reference
point resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V_DIFF, is
connected to the inverting input of the error amplifier through an
external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the 8-bit logic signal (VID)
into one of the discrete voltages shown in Table 3. Each VID
input offers a 45µA pull-up to an internal 2.5V source for use
with open-drain outputs. The pull-up current diminishes to
zero above the logic threshold to protect voltage-sensitive
output devices. External pull-up resistors can augment the
pull-up current sources in case the leakage into the driving
device is greater than 45µA.
EXTERNAL CIRCUIT
R_C C_{C COMP}
R_REF
C_REF
DAC
REF
FB
+
IDROOP
R_{FB VDROOP}
-
VDIFF
ISL6327A INTERNAL CIRCUIT
I_AVG
+
-
V_COMP
ERROR AMPLIFIER
V_OUT+
VSEN
+
V_OUT-
RGND
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 5. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of the output
voltage on the load current is often termed “droop” or “load
line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from the fast changes of the load-current demand.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
TABLE 2. VR10 VID TABLE (WITH 6.25mV EXTENSION)
VID4 VID3 VID2 VID1 VID0 VID5 VID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV (V)
0
1
0
1
0
1
1
1.6
0
1
0
1
0
1
0 1.59375
0
1
0
1
1
0
1 1.5875
0
1
0
1
1
0
0 1.58125
0
1
0
1
1
1
1
1.575
0
1
0
1
1
1
0 1.56875
0
1
1
0
0
0
1 1.5625
0
1
1
0
0
0
0 1.55625
0
1
1
0
0
1
1
1.55
0
1
1
0
0
1
0 1.54375
0
1
1
0
1
0
1 1.5375
0
1
1
0
1
0
0 1.53125
0
1
1
0
1
1
1
1.525
0
1
1
0
1
1
0 1.51875
0
1
1
1
0
0
1 1.5125
0
1
1
1
0
0
0 1.50625
0
1
1
1
0
1
1
1.5
0
1
1
1
0
1
0 1.49375
0
1
1
1
1
0
1 1.4875
0
1
1
1
1
0
0 1.48125
0
1
1
1
1
1
1
1.475
0
1
1
1
1
1
0 1.46875
1
0
0
0
0
0
1 1.4625
1
0
0
0
0
0
0 1.45625
13
FN6833.0
February 17, 2009