X98014_06 Datasheet, PDF (18/29 Pages) Intersil Corporation – 140MHz Triple Video Digitizer with Digital PLL

X98014
HSYNC_IN1
VSYNC_IN1
SOG_IN1
HSYNC_IN2
VSYNC_IN2
SOG_IN2
CLOCKINV_IN
XTAL_IN
XTAL_OUT
ACTIVITY 0x01[6:0]
&
POLARITY 0x02[5:0]
DETECT
HSYNC1
SLICER
0x03[2:0]
SOG
SLICER
0x1C
HSYNC2
SLICER
0x03[6:4]
SOG
SLICER
0x1C
CSYNC
SOURCE
0:
VGA1
00, 10,
HSYNC_IN
11:
HSYNC_IN
0x05[0]
1:
VGA2
SOG_IN
VSYNC_IN
0x05[4:3]
01:
SOG_IN
COAST
GENERATION
0x11, 0x12, 0x13[2]
0: ÷1
0x13
[6]
÷2
1: ÷2
PLL
0x0E through 0x13
SYNC VSYNC
SPLITTER
SYNC
TYPE
1:
SYNC
SPLTR
0x05[3]
0:
VSYNC_IN
Pixel Data 24
from AFE
HS
PIXCLK
Output
Formatter
0x18,
0x19,
0x1A
FIGURE 8. SYNC FLOW
HSYNC_OUT
VSYNC_OUT
R_P[7:0]
R_S[7:0]
G_P[7:0]
G_S[7:0]
B_P[7:0]
B_S[7:0]
DATACLK
DATACLK
HS_OUT
VS_OUT
XTALCLOCK_OUT
SYNC Processing
The X98014 can process sync signals from 3 different
sources: discrete HSYNC and VSYNC, composite sync on
the HSYNC input, or composite sync from a Sync-On-Green
(SOG) signal embedded on the Green video input. The
X98014 has SYNC activity detect functions to help the
firmware determine which sync source is available.
PGA
The X98014’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is:
Gain


V---
V


=
0.5 + -G-----a---i-1-n---7-C--0--o----d----e-
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1 V/V for GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per
line. In normal operation this means that there is a maximum
delay of one HSYNC period between a write to a Gain
register for a particular color and the corresponding change
in that channel’s actual PGA gain. If there is no regular
HSYNC/SOG source, or if the external clamp option is
enabled (register 0x13[5:4]) but there is no external clamp
signal being generated, it may take up to 100ms for a write
to the Gain register to update the PGA. This is not an issue
in normal operation with RGB and YUV signals.
Bandwidth and Peaking Control
Register 0x0D[3:1] controls a low pass filter allowing the
input bandwidth to be adjusted with three bit resolution
between its default value (0x0E = 780MHz) and its minimum
bandwidth (0x00, for 100MHz). Typically the higher the
resolution, the higher the desired input bandwidth. To
minimize noise, video signals should be digitized with the
minimum bandwidth setting that passes sharp edges.
18
FN8217.3
March 8, 2006