X98014_06 Datasheet, PDF (13/29 Pages) Intersil Corporation – 140MHz Triple Video Digitizer with Digital PLL

X98014
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME
DESCRIPTION
0x0D
AFE Bandwidth (0x0E)
0
Unused
Value doesn’t matter
3:1
AFE BW
3dB point for AFE lowpass filter
000: 100MHz
111: 780MHz (default)
7:4
Peaking
0000: Disabled (default) See Bandwidth and Peaking
Control section for more information
0x0E
0x0F
PLL Htotal MSB (0x03)
PLL Htotal LSB (0x20)
5:0
PLL Htotal MSB
7:0
PLL Htotal LSB
14 bit HTOTAL (number of active pixels) value
The minimum HTOTAL value supported is 0x200.
HTOTAL to PLL is updated on LSB write only.
0x10
PLL Sampling Phase (0x00)
5:0
PLL Sampling Phase Used to control the phase of the ADC’s sample point relative
to the period of a pixel. Adjust to obtain optimum image
quality. One step = 5.625° (1.56% of pixel period).
0x11
PLL Pre-coast (0x08)
7:0
Pre-coast
Number of lines the PLL will coast prior to the start of
VSYNC. Applies only to internally generated COAST
signals.
0x12
PLL Post-coast (0x00)
7:0
Post-coast
Number of lines the PLL will coast after the end of VSYNC.
Applies only to internally generated COAST signals.
0x13
PLL Misc (0x00)
0
PLL Lock Edge
0: Lock on trailing edge of HSYNC1 (default)
HSYNC1
1: Lock on leading edge of HSYNC1
1
PLL Lock Edge
0: Lock on trailing edge of HSYNC2 (default)
HSYNC2
1: Lock on leading edge of HSYNC2
2
Reserved
Set to 0.
3
CLKINV_IN Pin
Disable
5:4
CLKINV_IN Pin
Function
0: CLKINV_IN pin enabled (default)
1: CLKINV_IN pin disabled (internally forced low)
00: CLKINV (default)
01: External CLAMP (see Note)
10: External COAST
11: External PIXCLK
Note: the CLAMP pulse is used to
- perform a DC restore (if enabled)
- start the ABLC™ function (if enabled), and
- update the data to the Offset DACs (always).
When in the default internal CLAMP mode, the X98014
automatically generates the CLAMP pulse. If External
CLAMP is selected, the Offset DAC values will only change
on the leading edge of CLAMP. If there is no internal clamp
signal, there will be up to a 100ms delay between when the
PGA gain or offset DAC register is written to, and when the
PGA or offset DAC is actually updated.
0x14
0x15
6
7
DC Restore and ABLC™ starting 4:0
pixel MSB (0x00)
DC Restore and ABLC™ starting 7:0
pixel LSB (0x00)
XTALCLKOUT
Frequency
Disable
XTALCLKOUT
DC Restore and
ABLC™ starting
pixel (MSB)
DC Restore and
ABLC™ starting
pixel (LSB)
0: XTALCLK_OUT= f_CRYSTAL (default)
1: XTALCLK_OUT= f_CRYSTAL/2
0 = XTALCLK_OUT enabled
1 = XTALCLK_OUT is logic low
Pixel after HSYNC_IN trailing edge to begin
DC restore and ABLC™ functions. 13 bits.
Set this register to the first stable black pixel following the
trailing edge of HSYNC_IN.
0x16
DC Restore Clamp Width
(0x10)
7:0
DC Restore clamp Width of DC restore clamp used in AC-coupled
width (pixels)
configurations. Has no effect on ABLC™. Minimum value is
0x02 (a setting of 0x01 or 0x00 will not generate a clamp
pulse).
13
FN8217.3
March 8, 2006