X98014_06 Datasheet, PDF (12/29 Pages) Intersil Corporation – 140MHz Triple Video Digitizer with Digital PLL

X98014
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME
DESCRIPTION
0x05
Input configuration (0x00)
0
Channel Select
0: VGA1
1: VGA2
1
Input Coupling
0: AC coupled (positive input connected to clamp DAC
during clamp time, negative input disconnected from outside
pad and always internally tied to appropriate clamp DAC)
2
RGB/YUV
1: DC coupled (+ and - inputs are brought to pads and never
connected to clamp DACs). Analog clamp signal is turned off
in this mode.
0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale
analog shift for R, G, and B, base ABLC™ target code = 0x00
for R, G, and B)
0x06
Red Gain (0x55)
3
Sync Type
4
Composite Sync
Source
5
COAST CLAMP
enable
7:6
Reserved
7:0
Red Gain
1: YUV inputs (Clamp DAC = 600mV for R and B, 300mV for
G, half scale analog shift for G channel only, base ABLC™
target code = 0x00 for G, = 0x80 for R and B)
0: Separate HSYNC/VSYNC
1: Composite (from SOG or CSYNC on HSYNC)
0: SOG_IN
1: HSYNC_IN
Note: If Sync Type = 0, the multiplexer will pass HSYNC_IN
regardless of the state of this bit.
0: DC restore clamping and ABLC™ suspended during
COAST
1: DC restore clamping and ABLC™ continue during COAST
Set to 00.
Channel gain, where:
gain (V/V) = 0.5 + [7:0]/170
0x07
Green Gain (0x55)
7:0
Green Gain
0x00: gain = 0.5 V/V
(1.4VP-P input = full range of ADC)
0x08
Blue Gain (0x55)
7:0
Blue Gain
0x55: gain = 1.0 V/V
(0.7VP-P input = full range of ADC)
0xFF: gain = 2.0 V/V
(0.35VP-P input = full range of ADC)
0x09
0x0A
0x0B
0x0C
Red Offset (0x80)
7:0
Green Offset (0x80)
7:0
Blue Offset (0x80)
7:0
Offset DAC Configuration (0x00) 0
1
3:2
5:4
7:6
Red Offset
Green Offset
Blue Offset
ABLC™ enabled: digital offset control. A 1 LSB change in
this register will shift the ADC output by 1 LSB.
ABLC™ disabled: analog offset control. These bits go to the
upper 8 bits of the 10 bit offset DAC. A 1LSB change in this
register will shift the ADC output approximately 1 LSB (Offset
DAC range = 0) or 0.5LSBs (Offset DAC range = 1).
0x00 = min DAC value or -0x80 digital offset,
0x80 = mid DAC value or 0x00 digital offset,
0xFF = max DAC value or +0x7F digital offset
Offset DAC Range
0: ±1/2 ADC fullscale (1 DAC LSB ~ 1 ADC LSB)
1: ±1/4 ADC fullscale (1 DAC LSB ~ 1/2 ADC LSB)
Reserved
Set to 0.
Red Offset DAC LSBs These bits are the LSBs necessary for 10 bit manual offset
Green Offset DAC
LSBs
DAC control.
Combine with their respective MSBs in registers 0x09, 0x0A,
and 0x0B to achieve 10 bit offset DAC control.
Blue Offset DAC
LSBs
12
FN8217.3
March 8, 2006