ISL78235R5668 Datasheet, PDF (18/20 Pages) Intersil Corporation – Automotive 5A Synchronous Buck Regulator

ISL78235R5668
The compensator design procedure is as follows:
The loop gain at crossover frequency of f_c has a unity gain.
Therefore, the compensator resistance R₆ is determined by
Equation 6.
R₆ = ²----^-_G---^f--_M^c---^V---_-^o--_V--^C--_F--^o--_B--^R----^t = 13.710³  f_cV_oC_o
(EQ. 6)
Where GM is the transconductance, g_m, of the voltage error
amplifier and R_t is the gain of the current sense amplifier.
Compensator capacitors C₆ and C₇ are given by Equation 7.
C₆ = ^R-----_R^o---^C-₆----^o- = -^V-_I--_o-^o--_R-^C---₆--^o- ,C₇= max(-^R---_R-^c---^C-₆----^o-,_----_f--_s-¹--_R-----₆-)
(EQ. 7)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 7. An optional zero can boost the phase margin. _CZ2 is
a zero due to R₂ and C₃
Put compensator zero 2 to 5 times f_c:
C₃= _----_f--_c-¹--_R-----₂-
(EQ. 8)
Example: V_IN = 5V, V_O = 1.8V, I_O = 5A, f_SW = 2MHz, R₂ = 200kΩ,
R₃ = 100kΩ, C_o = 2 x22µF/10mΩ, L = 0.68µH, f_c = 100kHz, then
compensator resistance R₆:
R₆ = 13.710³  100kHz  1.8V  44F = 108k
(EQ. 9)
It is acceptable to use 107kΩas theclosest standard value for
R₆.
C₆ = ¹-₅---^.-_A-⁸---^V-_---₁--^--₀-⁴--₇-⁴---_k-^--_--^F-- = 148pF
(EQ. 10)
C₇= max(-¹---⁰----^m-₁----₀^---₇---^-_k--⁴-_---⁴---^----^F--,-_----_---₂----_M------_H----_z-¹---_--₁----₀---₇----_k---_------_)= (4.1pF,1.5pF) (EQ. 11)
It is also acceptable to use the closest standard values for C₆ and
C₇. There is approximately 3pF parasitic capacitance from V_COMP
to GND. Therefore, C₇ is optional. Use C₆ = 150pF and
C₇ = OPEN.
C₃= -_---₁----₀---₀----_k---_H-----_z1-----_---₂---₀---₀----_k---_--- = 16pF
(EQ. 12)
Use C₃ = 10pF. Note that C₃ may increase the loop bandwidth
from previous estimated value. Figure 45 shows the simulated
voltage loop gain. It is shown that it has a 120kHz loop
bandwidth with a 58° phase margin and 8dB gain margin. It may
be more desirable to achieve an increased phase and gain
margin. This can be accomplished by lowering R₆ by 10% to
20%.
60
40
20
0
-20
-40
-60
100
200
1k
10k
100k
1M
FREQUENCY (Hz)
150
100
50
0
-50
-100
-150
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 45. SIMULATED LOOP GAIN AND PHASE
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For the ISL78235R5668
the power loop is composed of the output inductor L₀, the output
capacitor C_O, the PHASE pins and the PGND pin. It is necessary
to make the power loop as small as possible and the connecting
traces among them should be direct, short and wide. The
switching node of the converter, the PHASE pins and the traces
connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The input capacitor
should be placed as close as possible to the VIN pin. The ground
of the input and output capacitors should be connected as close
as possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 5 vias ground connection within the pad for the best
thermal relief.
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FN8769.1
January 21, 2016