ISL78235R5668 Datasheet, PDF (17/20 Pages) Intersil Corporation – Automotive 5A Synchronous Buck Regulator

ISL78235R5668
Output Voltage Selection
The output voltage of the regulator is programmed with an external
resistor divider that is used to scale the output voltage relative to the
internal reference voltage (0.6V) and fed back to the inverting input
of the error amplifier FB pin (see Figure 42).
VOUT
VIN
16 15 14 13
VIN ₁
12 ^PGND
VDD ₂
11 ^PGND
PG ₃
ISL78235R5668
10 ^SGND
R₂
SYNC ₄
9 ^FB
56 78
R₃
line regulation. Figure 43 shows the small signal model of the
synchronous buck regulator.
^iin
V^in
+
^iL _LP
R_LP
ILd^ 1:D ^{Vind^}
RT
vo^
R_c
R_o
C_o
d^
T _i(S)
K
Fm
+
He(S)
Tv(S)
v^comp _-Av(S)
FIGURE 42. PROGRAMMING OUTPUT VOLTAGE WITH R₂ AND R₃
The output voltage programming resistor R₂ (from VOUT to FB)
will depend on the value chosen for the feedback resistor and the
desired output voltage of the regulator. The value for the
feedback resistor, R₃ (from FB to GND), is typically between
10kΩ and 100kΩ. R₂ is chosen as shown in Equation 4. Where
VFB = 0.6V and V_OUT is the output voltage.
R₂
=
R₃


V_{--V---O--F--U--B--T--}
–
1_
(EQ. 4)
There is a leakage current from VIN to PHASE. It is recommended
to preload the output with 10µA minimum for accurate output
voltage. For improved loop stability performance, add 10pF to
22pF in parallel with R₂. Check loop analysis before use in
application. See “Loop Compensation Design” for more
information.
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide a filtering
function to prevent the switching current flowing back to the
input rail. Two 22µF low ESR X7R rated ceramic capacitors in
parallel with a 0.1µF high frequency decoupling capacitor placed
very close to the VIN/VDD and SGND/PGND pins is a good
starting point for the input capacitor selection.
Loop Compensation Design
When COMP is not connected to VDD, the COMP pin is active for
external loop compensation. The ISL78235R5668 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current sensing circuit
in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant
and the system becomes a single order system. It is much easier
to design a type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
FIGURE 43. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Vo
R₂
C₃
R₃
VFB _-
VREF
GM
+
VCOMP
R₆
C₇
C₆
FIGURE 44. TYPE II COMPENSATOR
Figure 44 shows the type II compensator and its transfer function
is expressed as Equation 5:
A_vS= -^vˆ---c_vˆ---^oF---^m-_B----^p- = -_--_C-----₆----+-----_C-^G---₇--^M--_---_--^-_--^R-_R---³-₂-----+-----_R----₃----_ -_S--^--_-¹--₁---+--+---^----_{--------}^cS------_cS---^z------_p---¹-----₁--^_{---}-^---_¹--₁---+--+---^-----_{-------}^c-^S-----_c--_S-^z------_p---²------_2-^----_-
(EQ. 5)
Where,
_cz1 = -_R----₆--¹-_C-----₆- , _cz2 = -_R----₂--¹-_C-----₃- _cp1= _R--^C---₆-⁶--_C---+--₆--^C-_C----⁷-₇- _cp2= _C-^R----₃-²--_R--+---₂--^R-_R----³-₃-
Compensator design goal:
High DC gain
Choose Loop bandwidth f_c ~100kHz or less
Gain margin: >10dB
Phase margin: >40°
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FN8769.1
January 21, 2016