ISL78235R5668 Datasheet, PDF (15/20 Pages) Intersil Corporation – Automotive 5A Synchronous Buck Regulator

ISL78235R5668
PWM
PFM
PWM
CLOCK
I_L
0
16 CYCLES
PFM CURRENT LIMIT
LOAD CURRENT
NOMINAL +1.2%
V_OUT
NOMINAL
NOMINAL -1.2%
FIGURE 41. SKIP MODE OPERATION WAVEFORMS
Frequency Adjust
The frequency of operation is fixed at 2MHz when FS is tied to VIN.
The switching frequency is adjustable in the range from 500kHz to
4MHz with a resistor from FS to SGND according to Equation 1:
R_FSk = -_f-_O--²---_S²---⁰-_C----_---_k1---_H0----³-_z----_ – 14
(EQ. 1)
The ISL78235R5668 also has frequency synchronization
capability by connecting the SYNC pin to an external square pulse
waveform. The frequency synchronization feature will
synchronize the positive edge trigger and its switching frequency
up to 4MHz. The synchronization positive pulse width should be
100ns or greater for proper operation. The minimum external
SYNC frequency is half of the free running oscillator frequency
(either the default 2MHz when FS tied to VIN or determined by
the resistor from FS to SGND).
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 2.
The current sensing circuit has a gain of 120mV/A typical, from
the PFET current to the CSA output. When the CSA output reaches
the threshold, the OCP comparator is tripped to turn off the PFET
immediately. The overcurrent function protects the switching
converter from a shorted output by monitoring the current flowing
through the upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET is
immediately turned off and is not turned on again until the next
switching cycle. Upon detection of the initial overcurrent
condition, the overcurrent fault counter is set to 1. If on the
subsequent cycle another overcurrent condition is detected, the
OC fault counter is incremented. If there are 17 sequential OC
fault detections, the regulator is shut down under an overcurrent
fault condition. An overcurrent fault condition results in the
regulator attempting to restart in a hiccup mode within the delay
of eight soft-start periods. At the end of the 8th soft-start wait
period, the fault counters are reset and soft-start is attempted
again. If the overcurrent condition goes away during the delay of
8 soft-start periods, the output will resume back into regulation
point after hiccup mode expires.
Negative Current Protection
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side NFET, as shown in
Figure 3 on page 2. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both PFET and NFET are off.
A 100Ω discharge circuit in parallel to the NFET activates to
discharge the output into regulation. The regulator resumes
switching operation when output is within regulation. The
regulator will be in PFM for 20µs before switching to PWM if
necessary.
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After the soft-start period and a 1ms delay, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When the voltage at FB
pin drops 15% below 0.6V or rises above 0.8V, the
ISL78235R5668 pulls PG low. Any fault condition forces PG low
until the fault condition is cleared and after soft-start completes.
For logic level output voltages, connect an external pull-up
resistor between PG and VIN. A 100kΩ resistor works well in
most applications.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold (2.5V typical), the regulator is disabled.
Soft Start-Up
The soft start-up circuit reduces the inrush current during
power- up. The soft-start block outputs a ramp reference to the
input of the error amplifier. This voltage ramp limits the slew rate
of inductor current as well as the output voltage, so that the
output voltage rises in a controlled fashion. When VFB is less
than 0.1V at the beginning of the soft-start, the switching
frequency is reduced to 200kHz, so that the output can start-up
smoothly at light load condition. During soft-start, the IC operates
in the skip mode to support prebiased output condition.
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FN8769.1
January 21, 2016