ISL6227_07 Datasheet, PDF (18/28 Pages) Intersil Corporation – Dual Mobile-Friendly PWM Controller with DDR Option

ISL6227
The schematics for the internal compensator is shown in
Figure 38.
1.25pF
500K
TO PWM
COMPARATOR
4.4K
ISEN
1M 15pF
-
Vc ⁺
300K
0.9V
VSEN
FIGURE 38. THE INTERNAL COMPENSATOR
Its transfer function can be written as the following:
Gcomp(s)
=
1_----._-8_----5_---7_-----•_----1_----0_---⁵_{----⎝⎛--2}--------_π------^s--_f----_z------₁-----+-----1_{----⎠⎞---⎝⎛----2-------π}-----^s_{--f----z------2------+-----}1_{---⎠⎞-}
s
⎛
⎝
-------^s--------
2πf_p1
+
1_⎠⎞
(EQ.12)
where
f_z1 = 6.98kHz, f_z2 = 380kHz, and f_p1 = 137kHz
Outside the ISL6227 chip, a capacitor C_z can be placed in
parallel with the top resistor in the feedback resistor divider,
as shown in Figure 34. In this case the transfer function from
the output voltage to the middle point of the divider can be
written as:
Gfd(s)
=
-------^R-----²--------
R₁ + R₂
s^----(^--R^---s--₁^--R--|^--|^1--R^--C---₂^-z--)^--+-C^----_z^1----+-----1^--
(EQ.13)
The ratio of R₁ and R₂ is determined by the output voltage
set point; therefore, the position of the pole and zero
frequency in the above equation may not be far apart;
however, they can improve the loop gain and phase margin
with the proper design.
The C_z can bring the high frequency transient output voltage
variation directly to the VSEN pin to cause the PGOOD drop.
Such an effect should be considered in the selection of C_z.
From the analysis above, the system loop gain can be
written as:
Gloop(s) = G(s) • Gcomp(s) • Gfd(s)
(EQ.14)
Figure 39 shows the composition of the system loop gain. As
shown in the graph, the power stage becomes a well
damped second order system as compared to the LC filter
characteristics. The ESR zero is so close to the high
frequency pole that they cancel each other out. The power
stage behaves like a first order system. With an internal
compensator, the loop gain transfer function has a cross
over frequency at about 30kHz. With a given set of
parameters, including the MOSFET r_DS(ON), current sense
resistor R_CS, output LC filter, and voltage feedback network,
the system loop gain can be accurately analyzed and
modified by the system designers based on the application
requirements.
60
50
40
30
20
10 _VO/VC
0
-10
-20
-30
-40
-50
-60
100
1•10³
LC FILTER
COMPENSATOR
LOOP GAIN
1•10⁴
FREQUENCY (Hz)
1•10⁵
1•10⁶
FIGURE 39. THE BODE PLOT OF THE LC FILTER,
COMPENSATOR, CONTROL TO OUTPUT
VOLTAGE TRANSFER FUNCTION, AND SYSTEM
LOOP GAIN
Gate Control Logic
The gate control logic translates generated PWM signals
into gate drive signals providing necessary amplification,
level shift, and shoot-through protection. It bears some
functions that help to optimize the IC performance over a
wide range of the operational conditions. As MOSFET
switching time can vary dramatically from type to type, and
with the input voltage, the gate control logic provides
adaptive dead time by monitoring real gate waveforms of
both the upper and the lower MOSFETs.
Dual-Step Conversion
The ISL6227 dual channel controller can be used either in
power systems with a single-stage power conversion, when
the battery power is converted into the desired output
voltage in one step, or in the systems where some
intermediate voltages are initially established. The choice of
the approach may be dictated by the overall system design
criteria, or the approach may be a matter of voltages
available to the system designer, as in the case of PCI card
applications.
When the output voltage is regulated from low voltage such
as 5V, the feed-forward ramp may become too shallow,
creating the possibility of duty-factor jitter; this is particularly
relevant in a noisy environment. Noise susceptibility, when
operating from low level regulated power sources, can be
improved by connecting the VIN pin to ground, by which the
feed-forward ramp generator will be internally reconnected
from the VIN pin to the VCC pin, and the ramp slew rate will
be doubled.
18
FN9094.4
December 21, 2006