ISL1904 Datasheet, PDF (18/21 Pages) Intersil Corporation – Dimmable AC Mains LED Driver with PFC and Primary Side Regulation

ISL1904
ISL1903
IOUT
REFERENCE
AC
GENERATOR
RPU
VREF
VERR
_
FB
CFB1
CFB2
RFB2
R1
RFB1
R2
CFILTER
FIGURE 14. TYPE II EA CONFIGURATION
OVP
The ISL1904 has independent overvoltage protection accessed
through the OV pin. There is a nominal 20µA switched current
source used to create hysteresis. The current source is active only
during an OV fault; otherwise, it is inactive and does not affect
the node voltage. The magnitude of the hysteresis voltage is a
MONITORED
VOLTAGE
COPT
R1
R3
R2
VREF
20µA
10
1.5V ^_
FIGURE 15. OV HYSTERESIS
function of the external resistor divider impedance.
V_{ov(ri sin g)}
=
1.5
⋅
(_---R_-----1_-----+----R_-----2_----)
R2
V
(EQ. 16)
If the divider formed by R1 and R2 is sufficiently high
impedance, R3 is not required, and the hysteresis is:
ΔV = 20 ⋅ 10^–6 ⋅ R1
V
(EQ. 17)
signal could be filtered with a small capacitor placed between
the OV pin and signal ground. This technique does not work well
when the hysteresis is a current source because a current source
takes time to charge the filter capacitor. There is no
instantaneous change in the threshold level rendering the
current hysteresis ineffective. To remedy the situation, the filter
capacitor must be separated from the OV pin by R3. The
capacitor and R3 must be physically close to the OV pin.
OFFREF Control
The ISL1904 provides the ability to disable the output based on
the level of the control loop reference, set by the AC conduction
angle on the AC pin. Setting OFFREF to a voltage between 0 and
0.6V determines the threshold voltage that disables the output.
REFIN(off) = OFFREF – 0.100 V
(EQ. 19)
OFFREF allows the designer to disable the output at a
pre-determined load current to prevent undesirable behavior
such as at light loading conditions when there may be
insufficient current to maintain the holding current in a
triac-based dimmer. Setting OFFREF to less than 100mV disables
this feature. OFFREF has a nominal hysteresis of 50mV.
REFIN(on) = OFFREF – 0.050 V
(EQ. 20)
Quasi-Resonant Switching
The ISL1904 uses critical conduction mode PWM control
algorithm. Near zero voltage switching (ZVS) or quasi-resonant
valley switching, as it is sometimes referred to, can be achieved
in the flyback topology by delaying the next switching cycle after
the transformer current decays to zero (critical conduction
mode). The delay allows the primary inductance and capacitance
to oscillate, causing the switching FET drain-source voltage to
ring down to a minimal. If the FET is turned on at this minimal,
the capacitive switching loss (1/2 CV²) is greatly reduced.
Winding Current
FET D-S Voltage
If that does not result in the desired hysteresis then R3 is
needed, and the hysteresis is:
ΔV = 20 ⋅ 10^–6 ⋅ _⎝⎛R1 + R3 ⋅ ⁽---^R-----¹--_R---+--₂--^R-----²----^{)⎠⎞}
V
(EQ. 18)
If the OV signal requires filtering, the filter capacitor, Copt, should
be placed as shown in Figure 11. The current hysteresis provides
great flexibility in setting the magnitude of the hysteresis voltage,
but it is susceptible to noise due to its high impedance. If the
hysteresis was implemented as a fixed voltage instead, the
FIGURE 16. QUASI-RESONANT NEAR-ZVS SWITCHING
The delay duration is set with a resistor from DELADJ to ground.
Figure 8 on page 13 shows the graphical relationship between
the delay duration and the value of the DELADJ resistance. The
relationship is linear for resistance values greater than ~ 20 kΩ
18
FN8286.1
September 20, 2012