ISL1904 Datasheet, PDF (17/21 Pages) Intersil Corporation – Dimmable AC Mains LED Driver with PFC and Primary Side Regulation

ISL1904
The OC pin also provides cycle-by-cycle overcurrent protection.
The ON-time is terminated if OC exceeds 0.6V nominal. There is
~120ns of leading edge blanking (LEB) on OC to minimize or
eliminate external filtering.
Dimming
The ISL1904 supports both PWM and DC current modulation
dimming. In either case, the control loop determines the average
current delivered to the load.
The usual method of dimming an LED string is to modulate the
DC current through the string. DC current dimming is the lower
cost method, but results in a non-linear dimming characteristic
due to the increasing efficacy of the LEDs as current is reduced.
PWM dimming results in linear dimming behavior.
For PWM dimming, an external FET, controlled by PWMOUT, is
required to gate the drive signal to the switching FET. See “Typical
Application - Dimmable DC Input Boost Converter” on page 5 for
an example. When PWMOUT is high, the main switching FET
operates normally. When PWMOUT is low, the main switching
FET gate signal is blocked and the converter is effectively off.
This method is typically used when the LED string is not ground
referenced.
Another method uses an external FET to interrupt the LED load
current as shown in “Typical Application - Isolated Flyback with
PWM Dimming” on page 4.
Regardless of the dimming method used, the control loop
determines the average current delivered to the load. It does not
matter if the load current is DC or pulsed as long as the control
loop bandwidth is sufficiently lower than the pulsed current
frequency. The converter control loop and output capacitance
operate to filter and average the converter output current
independently of the actual load current waveform.
The dimming PWM and control loop are linked together such that
the PWM duty cycle tracks the main control loop reference
setpoint. If the control loop is set for 50% load, for example, the
dimming PWM duty cycle is set for 50%. The LED current will be
at 100% load for 50% of the time and 0% load for 50% of the
time, which averages to the 50% average load setpoint. See
Figures 7 and 9 for a graphical representation of the relationship
between the control loop reference and PWMOUT duty cycle. It
should be noted that the PWMOUT duty cycle is not allowed to go
to zero.
Control Loop
The control loop configuration is user adjustable with the
selection of the external compensation components. For
applications requiring power factor correction (PFC), a very low
bandwidth integrator is used, typically 20Hz or less. In other
applications, the control loop bandwidth can be increased as
required like any other externally compensated voltage mode
PWM controller.
Referring to Figure 13, the FET switching current flowing through
Rs, is applied to the OC pin of the ISL1904. The peak signal is
sampled, buffered, and output on IOUT as a PWM signal with a
gain of four and a duty equal to the complement of the converter
duty cycle (OUT). The voltage on IOUT, when averaged, is a scaled
representation of the maximum steady state output current, Io.
XFMR
ISL1904
OUT
OC
OC - IOUT
IOUT
PROCESSOR
AC
REFERENCE
GENERATOR
RPU
VREF
VERR
RS
_
FB
CFB
R1
RFB
R2
CFILTER
FIGURE 13. CONTROL LOOP CONFIGURATION
IOUT
=
8_-----⋅_---R_-----s_--
N_sp
⋅
I_o
V
(EQ. 13)
where IOUT is the average value of IOUT. IOUT must be scaled
such that at maximum output current Io is equal to the
maximum reference level (nominally 0.530V), while also limiting
the maximum peak primary OC signal to less than the
overcurrent threshold of 0.6V.
R_s
=
--------------------------------------------^V----^O----^C---------------------------------------------
2⋅
2
⋅
N_sp
⋅
I_o
C
L
⎛
⎜1
⎝
+
L^--L--_s^-p---⋅^--⋅-V^--N--_m^--s---pI--_N^---⋅-_r^--V_m^----o-_s^-_{⎠⎟⎞}
Ω
(EQ. 14)
where I_oCL is the output current limit threshold, V_OC is the
current limit threshold, and Rs is the current sensing resistor.
Once the value of Rs is determined, Equation 14 can be used to
solve for the level of OC at any steady state current and input
voltage when Io is substituted for Io_CL.
V_OC(SS) = R_s ⋅ 2 ⋅
2
⋅
N_sp
⋅
I_o
⎛
⎜1
⎝
+
L_--L--p-s---⋅_-⋅---NV_{----s-I--Np----r}⋅_--m--V_{---s-o-⎠⎟⎞}
V (EQ. 15)
where V_OC(SS) is the peak steady state value of OC corresponding
for the specific operating conditions.
As indicated previously, IOUT must be scaled properly prior to
connection to the FB input. Using Equation 13, and the value of
Rs obtained from Equation 14, the divider network to scale IOUT
can be determined.
The EA compensation depends on the bandwidth required for the
application. For PFC applications the BW is necessarily limited to
20Hz or less. For other applications, the BW may be increased as
required up to about 1/5 of the lowest switching frequency
allowed as described in “Oscillator” on page 14. For the low BW
applications a Type I compensation configuration is adequate.
For higher BW applications, a Type II configuration may be
required. Figure 13 shows the Type I configuration. Figures 13
and 14 show the Type I and Type II configurations, respectively.
17
FN8286.1
September 20, 2012