ISL6754 Datasheet, PDF (17/19 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL6754
maintains the current, which now circulates around the path
of switch UR, the transformer primary, and switch UL. When
switch LL opens, the output inductor current free-wheels
predominantly through diode D1. Diode D2 may actually
conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This condition persists
through the remainder of the half-cycle.
VIN+
UL
I_P
LL
UR
L_L
LR
D1
I_S
D2
VOUT+
RTN
VIN-
FIGURE 18. UR - UL FREE-WHEELING PERIOD
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
VIN+
UL
I_P
LL
UR
L_L
LR
D1
I_S
D2
VOUT+
RTN
VIN-
FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 L_LI_P2),
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Synchronous Rectifier Outputs and Control
The ISL6754 provides double-ended PWM outputs, OUTLL
and OUTLR, and synchronous rectifier (SR) outputs,
OUTLLN and OUTLRN. The SR outputs are the
complements of the PWM outputs. It should be noted that
the complemented outputs are used in conjunction with the
opposite PWM output, i.e. OUTLL and OUTLRN are paired
together and OUTLR and OUTLLN are paired together.
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 20. BASIC WAVEFORM TIMING
Referring to Figure 20, the SRs alternate between being both
on during the free-wheeling portion of the cycle (OUTLL/LR
off), and one or the other being off when OUTLL or OUTLR is
on. If OUTLL is on, its corresponding SR must also be on,
indicating that OUTLRN is the correct SR control signal.
Likewise, if OUTLR is on, its corresponding SR must also be
on, indicating that OUTLLN is the correct SR control signal.
A useful feature of the ISL6754 is the ability to vary the
phase relationship between the PWM outputs (OUTLL, OUT
LR) and the their complements (OUTLLN, OUTLRN) by
±300ns. This feature allows the designer to compensate for
differences in the propagation times between the PWM FETs
and the SR FETs. A voltage applied to V_ADJ controls the
phase relationship.
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 21. WAVEFORM TIMING WITH PWM OUTPUTS
DELAYED, 0V < V_ADJ < 2.425V
17
FN6754.1
September 29, 2008