ISL6754 Datasheet, PDF (10/19 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL6754
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by CT and a fixed 200µA internal current source.
The discharge duration is determined by RTD and CT.
T_C ≈ 11.5 ⋅ 10³ ⋅ CT
S
(EQ. 1)
T_D ≈ (0.06 ⋅ RTD ⋅ CT) + 50 ⋅ 10^–9
S
(EQ. 2)
T_SW
=
T_C + T_D
=
-----¹-------
F_SW
S
(EQ. 3)
where T_C and T_D are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, T_SW is the
oscillator period, and F_SW is the oscillator frequency. One
output switching cycle requires two oscillator cycles. The
actual times will be slightly longer than calculated due to
internal propagation delays of approximately 10ns/transition.
This delay adds directly to the switching duration, but also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very small
discharge currents are used, there will be increased error
due to the input impedance at the CT pin. The maximum
recommended current through RTD is 1mA, which produces
a CT discharge current of 20mA.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
D
=
---^T----^C-----
T_SW
(EQ. 4)
DT = 1 – D
(EQ. 5)
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle
peak overcurrent protection which provides fast response.
The cycle-by-cycle peak current limit results in pulse-by-pulse
duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the threshold,
the active output pulse is immediately terminated. This results
in a decrease in output voltage as the load current increases
beyond the current limit threshold. The ISL6754 operates
continuously in an overcurrent condition without shutdown.
The second method is a slower, averaging method which
produces constant or “brick-wall” current limit behavior. If
voltage-mode control is used, the average overcurrent
protection also maintains flux balance in the transformer by
maintaining duty cycle symmetry between half-cycles. If
voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
operation. The DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. Average current limit will prevent the
instability and allow continuous operation in current limit
provided the control loop is designed with adequate
bandwidth.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
The current sense signal applied to the CS pin connects to
the peak current comparator and a sample and hold
averaging circuit. After a 70ns leading edge blanking (LEB)
delay, the current sense signal is actively sampled during the
on time, the average current for the cycle is determined, and
the result is amplified by 4x and output on the I_OUT pin. If an
RC filter is placed on the CS input, its time constant should
not exceed ~50ns or significant error may be introduced on
I_OUT.
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
FIGURE 5. CS INPUT vs I_OUT
Figure 5 shows the relationship between the CS signal and
I_OUT under steady state conditions. I_OUT is 4x the average
of CS. Figure 6 shows the dynamic behavior of the current
averaging circuitry when CS is modulated by an external
sine wave. Notice I_OUT is updated by the sample and hold
circuitry at the termination of the active output pulse.
10
FN6754.1
September 29, 2008