ISL6316 Datasheet, PDF (17/29 Pages) Intersil Corporation – Enhanced 4-Phase PWM Controller with 6-Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current Sensing for VR10 Application

ISL6316
voltage under load can effectively be level shifted down so
that a larger positive spike can be sustained without crossing
the upper specification limit.
As shown in Figure 8, a current proportional to the average
current of all active channels, I_AVG, flows from FB through a
load-line regulation resistor R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as:
V_DROOP = I_AVG R_FB
(EQ. 8)
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate sample
current expression defined by the current sense method
employed.
V_OUT
=
V_REF
–
V_O
F
S
–



-I-^O-----^U----^T--
N
------R----^X-------
R_ISEN

R _{F B}
(EQ. 9)
Where V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current of
the converter, R_ISEN is the sense resistor connected to the
ISEN+ pin, and R_FB is the feedback resistor, N is the active
channel number, and R_X is the DCR, R_DS(ON), or R_SENSE
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to:
R_LL
=
--R----^F----^B--
N
-----R-----^X-------
R_ISEN
(EQ. 10)
Output-Voltage Offset Programming
The ISL6316 allows the designer to accurately adjust the
offset voltage. When a resistor, R_OFS, is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into OFS. If R_OFS
is connected to ground, the voltage across it is regulated to
0.4V, and I_OFS flows out of OFS. A resistor between DAC and
REF, R_REF, is selected so that the product (I_OFS x R_OFS) is
equal to the desired offset voltage. These functions are shown
in Figure 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
1_----._--6_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 11)
For Negative Offset (connect R_OFS to GND):
R_OFS
=
0_----._--4_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 12)
VCC
OR
GND
-
1.6V
+
+
0.4V
-
R_OFS
OFS
ISL6316
VCC
GND
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs during regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner. Supervising
the safe output voltage transition within the DAC range of the
processor without discontinuity or disruption is a necessary
function of the core-voltage regulator.
The ISL6316 checks the VID inputs six times every switching
cycle. If the VID code is found to have been changed, the
controller waits for half of a switching cycle before executing a
6.25mV step change. If the difference between DAC level and
the new VID code changes during the half-cycle waiting
period, no change to the DAC output is made. If the VID code
is more than 1-bit higher or lower than the DAC (not
recommended), the controller will execute 6.26mV step
change six times per cycle until VID and DAC are equal.
Therefore it is important to carefully control the rate of VID
stepping in 1-bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R_REF and C_REF, can be used. The selection of
R_REF is based on the desired offset voltage as detailed above
in Output-Voltage Offset Programming. The selection of C_REF
is based on the time duration for 1-bit VID change and the
allowable delay time.
17
FN9227.0
August 31, 2005