ISL6316 Datasheet, PDF (16/29 Pages) Intersil Corporation – Enhanced 4-Phase PWM Controller with 6-Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current Sensing for VR10 Application

ISL6316
TABLE 1. VR10 VID 6-BIT
VID4 VID3 VID2 VID1 VID0 VID5 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV
(V)
0
1
0
1
0
1
1.6000
0
1
0
1
1
0
1.5875
0
1
0
1
1
1
1.5750
0
1
1
0
0
0
1.5625
0
1
1
0
0
1
1.5500
0
1
1
0
1
0
1.5375
0
1
1
0
1
1
1.5250
0
1
1
1
0
0
1.5125
0
1
1
1
0
1
1.5000
0
1
1
1
1
0
1.4875
0
1
1
1
1
1
1.4750
1
0
0
0
0
0
1.4625
1
0
0
0
0
1
1.4500
1
0
0
0
1
0
1.4375
1
0
0
0
1
1
1.4250
1
0
0
1
0
0
1.4125
1
0
0
1
0
1
1.4000
1
0
0
1
1
0
1.3875
1
0
0
1
1
1
1.3750
1
0
1
0
0
0
1.3625
1
0
1
0
0
1
1.3500
1
0
1
0
1
0
1.3375
1
0
1
0
1
1
1.3250
1
0
1
1
0
0
1.3125
1
0
1
1
0
1
1.3000
1
0
1
1
1
0
1.2875
1
0
1
1
1
1
1.2750
1
1
0
0
0
0
1.2625
1
1
0
0
0
1
1.2500
1
1
0
0
1
0
1.2375
1
1
0
0
1
1
1.2250
1
1
0
1
0
0
1.2125
1
1
0
1
0
1
1.2000
1
1
0
1
1
0
1.1875
1
1
0
1
1
1
1.1750
1
1
1
0
0
0
1.1625
1
1
1
0
0
1
1.1500
1
1
1
0
1
0
1.1375
1
1
1
0
1
1
1.1250
TABLE 1. VR10 VID 6-BIT (Continued)
VID4 VID3 VID2 VID1 VID0 VID5 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV
(V)
1
1
1
1
0
0
1.1125
1
1
1
1
0
1
1.1000
1
1
1
1
1
0
OFF
1
1
1
1
1
1
OFF
0
0
0
0
0
0
1.0875
0
0
0
0
0
1
1.0750
0
0
0
0
1
0
1.0625
0
0
0
0
1
1
1.0500
0
0
0
1
0
0
1.0375
0
0
0
1
0
1
1.0250
0
0
0
1
1
0
1.0125
0
0
0
1
1
1
1.0000
0
0
1
0
0
0
0.9875
0
0
1
0
0
1
0.9750
0
0
1
0
1
0
0.9625
0
0
1
0
1
1
0.9500
0
0
1
1
0
0
0.9375
0
0
1
1
0
1
0.9250
0
0
1
1
1
0
0.9125
0
0
1
1
1
1
0.9000
0
1
0
0
0
0
0.8875
0
1
0
0
0
1
0.8750
0
1
0
0
1
0
0.8625
0
1
0
0
1
1
0.8500
0
1
0
1
0
0
0.8375
Load-Line Regulation
Some microprocessor manufacturers require a precisely-
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance, the
output voltage can effectively be level shifted in a direction
which works to achieve the load-line regulation required by
these manufacturers.
In other cases, the designer may determine that a more cost-
effective solution can be achieved by adding droop. Droop
can help to reduce the output-voltage spike that results from
fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL of
the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the output
16
FN9227.0
August 31, 2005