ISL6296_08 Datasheet, PDF (17/19 Pages) Intersil Corporation – FlexiHash™ For Battery Authentication

ISL6296
BIT
NAME
7:4
--
3:2 CSL[1:0]
1:0 SSL[1:0]
TYPE
R
RW
RW
TABLE 16. SECRETS SELECTION REGISTER (SESL)
DEFAULT
DESCRIPTION
0000 Unused
01
Coefficient Definition Secret Selection: Selects the authentication secret code word stored in
OTP ROM to be used as the coefficient definition code for the FlexiHash engine.
00: invalid selection
01: Authentication Secret Set #1
10: Authentication Secret Set #2
11: Authentication Secret Set #3
10
Seed Secret Selection: Selects the authentication secret code word stored in OTP ROM to be
used as the secret seed for the FlexiHash engine.
00: invalid selection
01: Authentication Secret Set #1
10: Authentication Secret Set #2
11: Authentication Secret Set #3
ADDRESS 0-0E/0F: GENERAL PURPOSE MEMORY
(INF1/2)
These address locations can be used to store information
like model ID, date code, and other cell information which
can be read by the host.
ADDRESS 1-00: MASTER CONTROL REGISTER (MSCR)
The Master Control Register is defined in Table 14. The
MSCR register can be both read or written by the host
through the XSD bus.
ADDRESS 1-01: DEVICE STATUS REGISTER (STAT)
The STAT register is defined in Table 15. All status bits will
be cleared upon a read to this register. The STAT is a
read-only register.
ADDRESS 2-00: SECRETS SELECTION REGISTER
(SESL)
This register must be written to re-load the hash engine with
secrets stored in OTP ROM prior to presenting a new
challenge code word input.
ADDRESS 2-01: CHALLENGE CODE INPUT REGISTER
(CHLG)
This register is used to input the 32-bit challenge code
generated by the host for device authentication. All four
bytes of the challenge code should be written sequentially to
this register, starting with the least-significant byte. After the
fourth challenge byte is received, the authentication code
generation process will start. This CHLG is a write-only
register.
ADDRESS 2-05: AUTHENTICATION CODE OUTPUT
REGISTER (AUTH)
This register is used to output the 8-bit authentication code
calculated from the 32-bit challenge code. The register
content may be read only once after each challenge code
word is written to the device. Subsequent read to this
register without a new challenge being input will result in an
error condition.
Applications Information
XSD Bus Implementation
There are two ways to implement the XSD host in a
micro-processor. One way is to use a spare Universal
Asynchronous Receiver/Transmitter (UART). A general
purpose input/output (GPIO) can be used if no UART is
available for the XSD communication. Refer to application
note AN1167 available from Intersil for more information
regarding how to implement the XSD bus within a
microprocessor.
Pull-Up Resistor Selection
Since there is an internal pull-down current on the XSD pin,
as shown in Figure 7, it is important to choose a pull-up
resistor value that is low enough so that the small amount of
pull-down current through the resistor does not cause the
bus voltage to droop below the V_IH specification under any
condition. 5kΩ is a typical resistance used for pull up.
Powered by XSD Bus
In applications that the device supply voltage is lower than
2.6V (such as an application powered by a single-cell NiMH
battery), or a device that has no power source at all, the
ISL6296 can be powered by the XSD bus. The application
circuit is shown in Figure 2. The condition for such
application circuit to function properly is that the bus pull-up
voltage is 3.3V or 5V. The bus pull-up voltage will charge the
capacitor C₁ through an internal ESD diode, as shown in
Figure 7. The ESD diode has 0.4V drop typically.
ESD Rating
The ISL6296 ESD specification is rated at 4kV of the human
body model. When the ISL6296 is used in a hand-held
accessory, higher ESD rating is typically required. External
components are required to enhance the ESD performance.
Additional Application Information
See Related Literature referenced on the first page for
additional application information.
17
FN9201.2
March 21, 2008