ISL6296_08 Datasheet, PDF (11/19 Pages) Intersil Corporation – FlexiHash™ For Battery Authentication

HOST
TX
Open-Drain
Port Pin
RX
ISL6296
V_DDH
V_DDD
R_PU
ESD
Diode
ESD
Diode
1.5μA 6pF
DEVICE
RX
TX
FIGURE 7. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS
XSD
tb
t0
t1
tg
glitch
1
0
Break
BT
FIGURE 8. THE BUS SIGNAL TIMING DIAGRAM
TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING
PARAMETER SYM
DESCRIPTION
MIN
TYP
Bit Time
BT_H x = 0.5, 1, 2, or 4
Deglitch period
tg
PW (Pulse Width) less than this will result in a frame error
173.6/x
‘1’ pulse width
t1_H PW in this range will be interpreted as a ‘1’ code
0.227
‘0’ pulse width
t0_H PW in this range will be interpreted as a ‘0’ code
0.591
‘break’ time
tb_H PW in this range will be interpreted as a ‘break’ command
1
NOTE: Unless otherwise stated, all pulse width (PW) referenced are with respect to an active-low pulse.
MAX
0.124
0.453
0.824
100
PARAMETER
Bit Time
‘1’ pulse width
‘0’ pulse width
‘break’ time
SYM
BT_D
t1_D
t0_D
tb_D
TABLE 3. DEVICE TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING
DESCRIPTION
MIN
TYP
x = 0.5, 1, 2, or 4
164.2/x 172.8/x
‘1’ code transmit pulse width
0.304
‘0’ code transmit pulse width
0.696
PW in this range will be interpreted as a ‘break’ command
1.391
MAX
181.4/x
UNIT
µs
BT_H
BT_H
BT_H
BT_H
UNIT
µs
BT_D
BT_D
BT_D
11
FN9201.2
March 21, 2008