ISL23328 Datasheet, PDF (17/20 Pages) Intersil Corporation – Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23328
Applications Information
V_LOGIC Requirements
V_LOGIC should be powered continuously during normal operation.
In a case where turning V_LOGIC OFF is necessary, it is
recommended to ground the V_LOGIC pin of the ISL23328.
Grounding the V_LOGIC pin or both V_LOGIC and V_CC does not affect
other devices on the same bus. It is good practice to put a 1µF
cap in parallel to 0.1µF as close to the V_LOGIC pin as possible.
V_CC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V_CC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
6Fh to 7Fh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
17
FN7902.0
August 19, 2011